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I thought the reason that there are so many different models (i3, i5, and i7, for example) is that the more defects it has, the more the surface that becomes unusable, thus reducing the amount of transistors in use (which is why i3 are less powerful than i5). Don't they technically have some sort of redundancy?

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The most obvious is that they have multiple cores, and it's easy to completely disable a non functional one.

Now can Intel be more granular than the core level, like running a core with some defect ALU, I really don't know.

What's publicly known from the binning process is that it involves disabling core, reducing total cache size, and finding the maximum working frequency.

The bottom line is that it requires more effort to deal with defects in complex logic, for DRAM they would reduce the total memory size.

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