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Comment by dnet | Hacker News Reader

I see that it uses Wiring, but I'd be interested what the minimum requirements are for a compatible implementation. For example, would it be possible to implement it without some serious bit hacking on an ATtiny? (For example, ATtiny2313 has 128 bytes of RAM -- bytes, not kilobytes.) I see that the source code has plenty of comments, but a specification be much more readable in a separate Markdown file or (GitHub) wiki page.

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Thank you so much for your feedback.

I think the first step on ATtiny compatibility can be ATtiny85 with a decent port on wiring. (I think will work also without external oscillator using only internal PPL clock tuned to 16mhz).

I am thinking to open a wiki defining the standard to enable people like you to build easily an implementation for a still not compatible device.

Why don't you open an issue on github and we will all speak together there :)?

Making it work for ATtiny85 would be very neat. I've never tried to run it at 16Mhz without an external oscillaror -- only 8Mhz. Would it be a big problem to run the network at half speed? (ie to make it configurable)

I am quite stuck in that, to get acceptable speeds the speed has to be known at compile time and defined with #define

I think can work at standard speed on Attiny at 16 mhz.

Done:

- https://github.com/gioblu/PJON/issues/12

- https://github.com/gioblu/PJON/issues/13

Thank you so much, I will write you on github! I hope you will give to PJON a try.

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