Show HN: A simple bare-metal Forth for the PDP-10
github.com
github.com
If you're not playing with 36 bits, you're not playing with a full DEC.
I wonder if there's a way to use the PDP-10's repeated indirect bit effective address calculation to efficiently thread Forth code, or implement higher level words like <BUILDS and DOES> by bunny-hopping through the CFA (Code Field Address)? [1]
It had a horizontal bitslice architecture, and separate independent busses for main memory, operand stack and return stack, so several forth words that did some stack manipulation, used the alu, and returned from a call, could all be collapsed into one instruction that accessed main memory, the operand stack, and the return stack at the same time!
http://www.forth.com/archive/jfar/vol3/no2/article38.pdf
https://users.ece.cmu.edu/~koopman/stack_computers/sec4_4.ht...
The NOVIX chip is way different that what you're doing, since it has its own instruction set and a pretty fancy compiler. The set of FORTH words it chooses as its instruction set is a good example of a minimal FORTH kernel.
Mitch Bradley's Forth (which evolved into Open Firmware) [1], which is a purposefully word-size agnostic dialect, had the decoratively named word @c@++ which pops an address and pushes the address incremented by one ("++") and the byte at ("c@") the initial address ("@"), and the corresponding word @c!++ which went the other way. On a PDP-10 Forth that address could be a sized byte pointer!
If you had a complete set of arbitrarily sized byte processing words, then you could implement your string words in FORTH on top of those, and use whatever byte size for strings you want!