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Comment by andmarios | Hacker News Reader

Today a group of passionate undergraduates (guesstimate about 24 people) could probably design and build the schematics for the mask from ground up (not copying) as a semester project without neglecting the rest of their courses. The theory, the course material and the free tools (e.g for CAD and simulation) are that good!

44 years ago though, only a few talented engineers worldwide could implement it. :)

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I would guess even less than 24. Today you can write your structural Verilog implementation, run an automatic mapping to a PDK standard cell library, and simulate to verify. The hardest part might be floor planning for something like that today. The placement and routing can all be automagical, and you won't have any timing closure issues at these speeds. I'd guess a single student could do it if sufficiently motivated. And, with CMP or MOSIS you could have it manufactured on a 350nm CMOS process by AMS for $2200 (20-25 pcs).

Is it really that cheap? I was just looking into this a little and I thought it was more like $10-20k for a dozen large-ish CMOS process. Got a link to pricing details for stuff in the ballpark you gave?

24 people for doing the work Intel's engineers did. That is given the ISA and some hints (e.g a list of components they are going to need), to start from basic components and boolean expressions, convert them to CMOS circuits by hand and then draw them efficiently in a software like Magic.

I designed a functional replica of the 4004 using 74-series logic in my spare time while I was doing an undergraduate degree in Business during 2009-ish.

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