Skyscraper-style chip design boosts electronic performance | Hacker News Reader

Skyscraper-style chip design boosts electronic performance

news.stanford.edu

57 pointsingve13 comments

> suburban-style layouts create long commutes and regular traffic jams in electronic circuits

> millions of "vias," which play the role of tiny electronic elevators

Is it unreasonable to suggest that maybe there is such a thing as trying too hard to avoid scaring people with technicalities?

I mean, I get it, they made a neat skyscraper-versus-suburban analogy. Fair enough. But why not "just as suburban layouts in cities can mean long commutes and regular traffic jams, suburban layouts in chips can mean signals take longer to get from one place to another" or something?

I only skimmed the thing a bit, but how do they deal with heat exactly? Water cooling at every level?

It also kinda depends on the heat generated; I can imagine that this system allows for lower power consumption, which is equivalent to lower heat production.

FTFA:

"Just as skyscrapers have ventilation systems, N3XT high-rise chip designs incorporate thermal cooling layers. This work, led by Stanford mechanical engineers Kenneth Goodson and Mehdi Asheghi, ensures that the heat rising from the stacked layers of electronics does not degrade overall system performance."

Paper about that:

https://www.researchgate.net/publication/263004944_Phonon_sc...

Since these are stacked solid layers, heat isn't really "rising" though, is it?

maybe that's what the orange layer is which I assume is copper

I was in a 3DIC research group for ~2 years. We were mainly trying to build heat models for stacked chip designs to investigate this issue.

Another group that was looking at architecture was primarily relying on placing low power density devices on the lower levels of the chip (with worse heat dissipation) and the high-power devices at the top (with better heat dissipation), though I never saw the results of their finished design.

Ultimately though, heat is the primary issue with 3DIC. Assuaging the memory bottleneck by drastically increasing bandwidth at the cost of significantly more heat.

Not was AMD doing something similar ?

Yes indeed, the HBM memory in the latest AMD GPUs is stacked.

This press release is extremely frustrating, by the way, because it's full of fluff and hype. Through-silicon vias have been in discussion for a long time (and, as you said, are even in production already). Apparently, this team uses different materials (carbon nano-tubes). This is potentially interesting, but I'm very sceptical. Certainly, any claim of "factors of thousands" is just ridiculous. Wires are a significant part of delays on chips, but having shorter interconnects isn't going to speed up the switching time of transistors, which would become a bottleneck again.

The industry has been abuzz about these types of structures for years. It would be interesting to see if this is practical at scale: making millions of these types of chips per month with a high yield.

I think 3D-nand can be considered a practical use of such structures.

System on a chip is already able to achieve much of this. Without having to completely retool. It's not impossible to combine memory with CPU and GPU on one chip. This is one way in which computers have been getting smaller and have been using less resources.

I imagine this will still be useful though.

CNT (carbon nanotube transistor) is an unfortunate acronym. I can't imagine explaining that to my Mother.

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