RISC-V: Free Core, Some Assembly Required
eetimes.com
eetimes.com
Security Researcher Joanna Rutkowska just released a concept for a stateless laptop, http://blog.invisiblethings.org/2015/12/23/state_harmful.htm....
A fully Trusted computing base all and a secure architecture for application in the user level.
Lets make the future happen.
You can find his slides here (http://riscv.org/workshop-jan2016.html).
re cores
They don't appear to have floating point. That a pre-requisite for quite a few accelerator cases. Also could help explain how many he fits in there at what performance.
re FPGA
BOOM! I was thinking it was an UltraScale or Achronix given the numbers. So, that was a hit.
re NOC
Probably the most exciting thing there. I'm guessing he's going to license it. Might be able to use it in open projects or even ASIC's depending. I lack the expertise to speak on the latter except to say that the existence of EDA companies specializing in NOC generation means such a thing might be useful.
Also, good to know we can hit this kind of performance on an UltraScale. Makes me more hopeful about what can be achieved with an open 45nm or 28nm FPGA once we get them. Archipelago is progress in that area at 45-65nm already.
Plenty of stuff can get away with integer-only. Massive numbers of Xilinx DSP48 on a FPGA is pretty common.
When did FreeBSD become a Linux variant?
I would imagine my answer is the same as yours: never.
Just add the phrase to your indicators of poor and non-fact checked journalism. It helps tell if the author, article, and publication have any real value.
This is for embedded users, who typically add the processor chip to their own products, i.e. they are not intended to be end-user personal computers for general purpose use.
That's why ARM has the Intergrator/Versatile series of dev boards. Back in the day, MIPS had the Maltas.
Thats where I'm going wrong..