The future of computers – Part 1: Multicore and the Memory Wall (2011)

Nice overview on modern CPU limitations but I find it more interesting that the continual pitching of Venray Technology didn't seem to pan out. Not much online since around 2012. I wonder what went wrong with their idea to integrate CPUs onto DRAM. Weird architectures usually fail I guess.

This is a classic, the folks at Sandia are really interesting to talk to about computer architecture, one of the few places where solid research continues.

The interesting thing for me when I got to Google was understanding how the entire Map / Reduce paradigm worked. It really manages to greatly increase the amount of compute you can apply to a problem with a fairly painful restructuring. An interesting debate broke out about HPC (High Performance Computing) vs MPC (Massively Parallel Computing) and whether or not the architecture was irrelevant to the problem. Put specifically could a problem be expressed as an HPC problem, and then tranformed in some way to be expressed as an MPC problem. There is a pretty nice PhD in computer science in there somewhere, combining Amdahl's law with the theory of computation.

Generally most folks started in the "some things can't be done by map reduce" camp but over time more and more things have been shown to be doable that way, especially if you let the intermediate results float around inconsistently. I've always felt that combinators[1] had a role to play here. Sort of like the Z transform in signal theory, if you can decompose the problem into a set of combinator operations, is seems like you should be able to convert it from and HPC algorithm to a MPC algorithm. Just a conjecture as far as I can tell though.

[1] https://en.wikipedia.org/wiki/Combinatory_logic#Combinatory_...

Whoever posted this, thanks! I started looking into Venray Technologies. The latest paper series on their site is dated 2014: http://www.edn.com/design/systems-design/4429530/Two-Views-o...

These articles date from 2011 and 2012. They are an interesting snapshot of CPU architecture and implementation issues, but are already somewhat out-of-date to very out-of-date.