On the BF-538 that we were using, there are three of them and we needed them all. Since each one can only buffer a single incoming or outgoing byte at a time, there's a lot of interrupt-handling overhead with all of the RISC-style registers that need to be saved on each incoming byte.

We were already using two of the SPORTs and both DMA engines for hard real-time transmit and receive signal processing with microsecond-scale deadlines, so they weren't available to offload the UARTs. But since the UARTs have such tiny hardware buffers, their interrupts have to be very high priority in order to avoid dropping characters.

On a different project we were trying to build a very-low-power system around one of their new (at the time) BF52X parts, which had new low-power states for extended sleep. Except in the 0.0 version of the chips, those low-power states simply didn't work. An updated errata sheet was published a week or two later documenting that the processor couldn't be woken up once put to sleep.