It should be possible to write the majority of the code for an FPGA in a generic fashion and get the tools to infer things like RAM's by the way the Verilog or VHDL is written. Ideally, I think you should only have FPGA specific blocks in the very toplevel of a design and the majority of the design should be agnostic to the FPGA architecture. For example if you write your code like this:

  reg [31:0] mem[0:1023];
  
  always @(posedge clk) begin
    rd_data <= mem[rd_addr];
    if (wr_en)
      mem[wr_addr] <= wr_data;
  end

Then tools like vivado, quartus, synplify will infer a 1k x 32bits ram.