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You just reminded me of the days of Pascal/Modula/Oberon in Europe and C in US.

My impression was more Verilog in academia, VHDL in industry.

My impression is VHDL for defense contractors, verilog for commercial.

I did VHDL in academia, in Europe.

There's very little VHDL in industry.

VHDL == IBM and Europe.

France is the most VHDL country in the world.

Hopefully VHDL dies a terrible death and SystemVerilog becomes the defacto standard, which it is already well on its way of becoming. It is way more powerful, especially for Verification. UVM is now the one true standard for verification.

Australia is a mix between the two