Samsung Announces 512GB NVMe SSD That's Smaller Than a Stamp

The biggest consideration in this is the NAND bus loading on the controller. Typically a controller has 4-16 NAND buses. Each bus is about 16 IO pins (8-bit bus plus control signals) Each bus can drive 8 NAND die at full speed. By lowering the speed, you can drive 16 NAND die. With more NAND buses at high speed you have to worry about power routing and signal integrity issues so there is a limit to this. Typically each NAND package has 4-8 NAND die inside it so commonly you will see one NAND package per channel. Also you need to scale the DRAM with NAND capacity usually linearly. What happens in the end is the total number of channels is fixed by the number of die per channel varies from 2-8 dies. With each generation, the capacity of a single die increases. To increase beyond this, you general reduce the clock speed on the NAND bus which explains why the higher capacity SSD have slightly slower performance.

There has been some effort to switch NAND to serial protocol to lower IO count but it hasn't caught on. What Samsung is doing with multi die packages is very common (one company I worked for did it 10 years ago) but there are concerns with signal integrity and thermal limits to consider. It will generally have slower performance than the full models or use power throttling to keep within limits (good for burst workloads.)