Transistors Will Stop Shrinking in 2021, Moore’s Law Roadmap Predicts
spectrum.ieee.org
spectrum.ieee.org
Moore's law made most higher level hardware architecture innovation almost meaningless. Developing new kinds of parallel computers (Gray, Thinking Machines) was dead end when conventional computers made from Intel chips reached the same level in few years without specialized software.
Things have already changed. First specialized Graphics processors and now GPGPU are the first break from the normal. GPGPU's technology is one level up from lithography and silicon chemistry. It's different architecture and different programming paradigm. This will be the first time Intel is not going to shake it off with faster GPU.
We should expect more higher level hardware innovations. Integrating GPU functions into DRAM chips might be the next step.
http://www.micronautomata.com/
They might be missing the boat by not releasing cheap entry level hardware platform, ~$20 ddr3/4 stick.
[1] As I suppose we all are. C'mon we're talking about predicting the future here.
[2] If you want a practical example, look at the PS/3 Cell processor. I can't claim to have done any 'native' programming for the PS/3, but I've heard (from very clever people that I trust) that it was quite alien and required radically different program structure from what one is used to. And that architecture isn't even that different from 'normal' architectures.
I only mean to extend your timeline. I don't think my observations change your conclusion.
The new report embraces these trends, predicting an end to traditional scaling—the shrinking of chip features—by the early 2020’s. But the idea that we’re now facing an end to Moore’s Law “is completely wrong,” Gargini says. ... If a company really wanted to, Gargini says, it could continue to make transistors smaller well into the 2020s, “but it’s more economic to go 3-D. That’s the message we wanted to send.”
This is not to say that I am disagreeing with you on the switch-back-to-2d front, but I don't think we have much further to go on the 2d-density front.
It remains to be seen we still have that 12 years of efficiency available to us after building 3D chips. I can easily imagine that heat distribution would be a real problem.
Given how much of a problem it already is in 2D where the entire die area simply radiates "up and out", I think that head might be the real problem. I don't know how one would build a 3D embedded heat-sink, you know, something like this with the transistors and and connective mesh all around [1]. Maybe it looks like a Menger sponge [2], but that looks tough too! :-)
[1] https://s3.amazonaws.com/s3-blogs.mentor.com/robinbornoff/fi...
The thing is - it's expensive.
But than we can use this to build logic with memory on top ,and get huge bandwidth - and in multicore systems you could 100x performance in some algorithms , with easier programming. But this will be expensive.
But than we could start using those systems, building an ecosystem around them, generate money - and slowly, generation by generation with a moore's law like race, work on building photonics to greatly decrease power consumption - and hence cost.
That's at least the plan in [2].
Also relevant: ST microelectronics is in the final stages of opening a leading edge, commercial photonics fab.
[1]https://www.helpnetsecurity.com/2016/03/11/microfluidic-cool...
Now we just need to find a way to build those microchannels stacked at every other layer or so without building fluid junction popping back-pressure! :-)
Or maybe just plan on doubling down on photonics (your #2 suggestion); that certainly makes switching energy (and heat) go way waaay down.
I know if it was that easy we would already be doing it, but I'm hoping somebody knows why. Probably because interfacing the grown diamond to silicon creates interface stress that leads to cracking or...some other reason... :: mutters ::
3D stacking is mostly useful for parts that don't generate much heat. The inner layers have cooling problems. Flash memory, yes; CPUs, no.
Moore's Law was about increasing area density of transistors on a chip. Transistors got smaller and faster. Fabs got more expensive at each shrink, though. For a long time, the cost advantages of the shrink were a win over the increased fab cost. But that's ended. Fab cost ended up dominating the industry. There are only four high-end fab companies left.
The question for years is which limit would dominate - fab cost, heat dissipation, or, ultimately, the size of atoms and electrons. The first two are being reached now. Flash devices are already down to 10-20 significant electrons per storage cell, so there's not much room left there.
Atoms, electrons, and photons are just too big. There's no longer plenty of room at the bottom, as Feynman put it.
Agreed that Moore's law was about increasing density of transistors on a chip - but you can do that in various ways. The article was clear to state, "Moore’s Law, he emphasizes, is simply a prediction about how many transistors can fit in a given area of IC—whether it’s done, as it has been for decades, in a single layer or by stacking multiple layers."
The potential impact is game-changing. I really wonder how this is going to shape where investments in IT go.
Hence why the explosion in IoT nowadays, that is nothing new. Everyone with some EE background has been playing with microcontrolers since the early 2000.
However we have reached a point where to make such tiny computers, more powerful than any of my PCs at the university, is ridiculously cheap.
A computer like the Arduino used to cost more than 100 euros back in the day, now I can buy one for 5 euros and who cares if it burns.
On the other side of the spectrum we have CPUs like the Nvidia Titan X, which 99% of the computing population can barely make it get out of idle state.
So unless one is an heavy gamer, doing Fintech, VR or AI research there is hardly anything new processors can offer over the existing computing workloads.
So I guess it isn't stop shrinking as such, but also if it will still be economically viable to continue that route until a new computing paradigm emerges (e.g. Quantum or whatever)
Hopefully we'll start to see even more emphasis on optimisation, possibly revived interest in Asm while compilers catch up... and then realise just how efficient software can really be.
The developer mindset needs to change as well. I seldom here people wondering about the sheer computing power of the systems they use.
Many developers also seem to get a kick out of building complex systems (with (most of the time too) many abstraction layers burning cpu cycles) - because they seem to believe building complex things somehow means having control over complexity - but I'm not sure about that.
I wish we had a better, higher level, cross-platform access to SIMD.
https://developer.mozilla.org/en-US/docs/Web/JavaScript/Refe...
Add a ton of transistors to intelligently prefetch and cache will in some cases decrease those 225 CLKs.
A great deal of transistors are added to cache and cache intelligence to get around the terrible latency of DRAM.
The difficulty is in getting all the features you want within the space provided while adhering to the laws of physics.
[1] http://www.slideshare.net/dragonpradeep/carry-look-ahead-add...
Modern CPUs can execute several instructions per clock cycle doing things like this.
There are more ways to speed up your CPU, like identifying instructions that can be executed independently and issue them in parallel, use caches to speed up loading, etc.
1) Smaller circuits (used to?) have less capacitance and smaller voltages. Smaller voltages and capacitance enables higher clock-rate with same power consumption (chips don't melt)
2) Spending more transistors for pipelines and multiple execution units in the same core speeds up the processing. Single instruction takes at least five clock cycles from start to finish. With pipelines it's possible to finish one instruction per cycle. With multiple execution units it's possible to finish more than one instruction per cycle. This all from a single core.
3) Cache. Lots of it, different levels. Accessing external memory is very slow. Main cache reference takes about 1 ns. Main DDR MEMORY reference takes 100 ns. Waiting for 100 ns. wastes cycles. Adding prefetching etc. is yet another chunk of transistors.
[1] https://en.wikipedia.org/wiki/Carry-lookahead_adder [2] https://en.wikipedia.org/wiki/Binary_multiplier
When Mr. Moore put his law out there 50+ years ago, perhaps the concept of number/size of transistors was effectively a proxy for computing power, or perhaps even more true, no one saw a difference, or cared to see a difference between the two. Since Mr. Moore is still around, I would love to have his feedback about this- I guess, like Woody Allen's character pulling in Marshall McLuhan in Annie Hall.
Enough of the aside, though: since 1965, much has been learned on the hardware and software sides, industries have grown and shrunk, and we are now able to have debates that - at least somewhat - bifurcate the issue of size/density of hardware from the issue of the somewhat more intangible computing power.
Sure, these things are huge today, but we have now in our pockets more power than was available in a Cray super computer from the 80s.