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I'm not sure why the output is passed in at the start (I'm guessing it's like an out parameter in C#) and I don't understand what @(*) is, but that's surprisingly readable.

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It's exactly like an out parameter. HDL modules tend to have a lot more outputs, partly because you can't easily group them into structures.

The main things that trip people up in Verilog coming from programming are the difference between synthesis and simulation, and the intrinsic parallelism with the two kinds of assignment operator.

There are all kinds of idioms that are syntactically valid Verilog that cannot be compiled to hardware. Usually you only use these while constructing a "testbench" to drive the simulated hardware.

There are also two kinds of assignment: = and <=. So for example, starting with a being set to 1 and b being set to zero:

b = a; c = b+1;

results in c being set to 2.

always @(posedge clk) b <= a; c <= b+1; end

results in b being set to a and c being set to 1: the value of b on the previous cycle plus 1. It also causes flip-flops to be inferred to hold b and c.

(Note that <= behaves differently depending on what's in the sensitivity list, which is also potentially very confusing!)

If I were still doing HDL design I'd advance my plan for modern object(bus)-orientated friendly HDL..

The output isn't really "passed in". Verilog doesn't have an idea of variables, it replaces what traditionally might be variables with "ports" (think the pins on a chip). So, input and output ports must all be defined as part of the module declaration.

The @(*) syntax is what's called the sensitivity list, it's saying that the state of the module should be recalculated whenever any of the inputs change. Other possible values might include something like @(posedge clk) if you have a clock signal called "clk" and you only want the outputs of the module to update on the rising edge of the clock signal. This is dramatically oversimplifying the insanely complex world of HDL, but it's ultimately not /that/ hard if you know your computer architecture fundamentals.

Verilog isn't a programming language. It is a hardware description language. It is used to describe the behavior of hardware. The output isn't "passed" out at the beginning. Rather, That line is indicates that there is an output and what it's name is. The @() indicates a sensitivity list. The block below is evaluated whenever the states of any signal in the sensitivity list are changed. The * is a wildcard character and signifies any signal in the block below. That feature was added in Verilog2001. Before that, you had to manually list any signal you wanted in the sensitivity list.

> Verilog isn't a programming language. It is a hardware description language. It is used to describe the behavior of hardware.

In short, coding in verilog is like creating a schematic of the circuit.

You can write Verilog as schematic-like description, but there is a higher-level of modeling supported by synthesis tools that doesn't look quite so netlist like.

Nitpick: Verilog is a programming language (see especially testbenches) with syntax and a runtime geared towards modeling hardware. It allows simple creation of lightweight shared-everything threads (called processes, confusingly, and they are not OS threads or processes, they are local to the language runtime) which are used to model concurrent hardware. It has its own built-in scheduler that decides when to run each thread. It has numerous synchronization methods and events (wait, @, #12ns, etc.) in addition to plain-old shared memory that threads use to coordinate with each other, and block and trigger thread execution. When modeling digital circuits a single shared-memory variable, usually named clock or clk, is the one variable most of these threads synchronize to.

Mostly hardware designers get away without thinking about all those above details in those terms, but sometimes you get bit by them (race-conditions between threads can occur, sadly) and it helps to understand it.

All programming is modeling of some sort or another.

Yeah, I haven't had the opportunity to use Verilog but it does seem very readable!

I want to kind of give this library a similar direction. It's in its infancy at the moment :P

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