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Comment by vvanders | Hacker News Reader

I'd actually argue an FPGA/CPLD is a slightly better approach, simply because you have block memory that acts very much like "cache" and makes it abundant why system memory is so much slower.

Since you have timing statistics it also makes it really easy to demonstrate pipelining and many other modern "quirks" of processors that have a large impact on performance.

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The barrier to entry in the FPGA world is tooling and expression. If that hurdle is solved then I'd be all for it. It will usher a new era of electrical engineering design that is as cheap as software desgin making it practical for students to try EVERYTHING on their own.

To conduct similar experiments as I have with computer in electronics (as I'd like to do one day so I can get to the same place I am in electronics as I am in computer science) I'd need to spend thousands of dollars on chips and parts.

>"The barrier to entry in the FPGA world is tooling and expression"

Regarding tooling, I'd say it's not quite the barrier it used to be, now that Project IceStorm exists.

http://www.clifford.at/icestorm/

If you're writing VHDL or Verilog then it's for electrical engineers, not humans. The barriers include bad description languages.

You should just have an EDA system. It will take time for pros to use but will be easy for beginners (especially considering that the output of the EDA will usually be what they did)

The GP mentioned 'tooling and expression', I mentioned tooling, you're mentioning expression.

Aside from that, other HDLs than just Verilog and VHDL do exist, such as Chisel and CλaSH:

https://chisel.eecs.berkeley.edu/

http://www.clash-lang.org/

Also, whilst I'm sure open source EDA tools could be improved, some of the basic building blocks exist, it appears to be more of an issue of packaging than availability. Seems like EDA tooling is a niche that a specialist Linux distro could fill (if tutorials are also provided).

>The barrier to entry in the FPGA world is tooling and expression.

Re: tooling, both major vendors of FPGAs have free basic versions of their tools (e.g. Xilinx's Vivado and ISE Webpack) and supported development boards are available for $99 or less (e.g. Digilent's Arty Board).

Re: expression, both Verilog and VHDL permit gate level modeling. Verilog even has gates as language primitives.

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