FeFETs: How this new memory stacks up against existing non-volatile memory | Hacker News Reader

FeFETs: How this new memory stacks up against existing non-volatile memory

semiengineering.com

94 pointsSemiTom22 comments

A link to the paper mentioned in the article (paywall/institution access): http://ieeexplore.ieee.org/document/7838397/

TL;DR - Much lower erase time than NOR Flash (3 orders of magnitude), 1/3 voltage required for write/erase, all other parameters typically the same

The results from the paper are summarized as follows:

- Cell size is comparable to current NOR Flash (0.045 um^2)

- Endurance is also comparable (~10^5 cycles)

- Estimated 10 year retention @105C, compared to 150C for NOR

- Read time <25 ns, versus <10 ns

- Write time around 500 ns (1/2 of NOR)

- Erase time around 500 ns, compared with 10^6 ns for NOR (!)

- Energy consumption not yet measured, but claimed less than Flash

- Max voltage of 4.5V, versus 12V for Flash

Thanks for the summary.

With the same endurance but much lower erase time you could run out of write cycles in the blink of an eye?

You forgot the most important stuff: it scales well with various technology nodes and processes, requires much less mask layers than flash and it is much more cost effective.

Edit:also , they mentioned an ncfet transistor for general use.since this transistor remember his state, you may not have to power it in sleep mode(whole circuit or partial), and thus could get zero leakage current!

>Edit:also , they mentioned an ncfet transistor for general use.since this transistor remember his state, you may not have to power it in sleep mode(whole circuit or partial), and thus could get zero leakage current!

Um, no, that's not the point of the NC FET. The "negative capacitance" aspect of the ferroelectric material means that the NC FET can switch on or off faster, reducing power wasted in the switching process, and therefore allow chips to run cooler.

See https://phys.org/news/2011-09-ferroelectrics-pave-ultra-low-... for a general explanation or https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-... for a technical explanation.

In [1] , they build a non-volatile flip-flop out of a ncfet.

[1]section 5.3 , https://www.google.co.il/url?sa=t&source=web&rct=j&url=http:...

With regards to energy consumption, from the article:

> FeFETs, according to FMC, provide fast switching at low power. FMC says it provides a 1,000X improvement in per-bit write energy.

They didn't tell one thing: how long can it sustain data unpowered at what BER?

What is the difference between writing and erasing here?

You can only write once to every block, then you have to erase it completely before reusing. This causes so-called write amplification, in the extreme meaning that changing one bit requires erasure and rewrite for the whole 4K block. See here for deeper explanation: https://www.extremetech.com/extreme/210492-extremetech-expla...

edit: Typically the SSD has a pool of empty blocks, so in actuality, rewrite is done to one of these blocks and the previously used block is erased and returned to the pool.

Thanks!

> Typically the SSD has a pool of empty blocks

So erase time (the main advantage of this new FeFET technology) does not matter much in practice?

My guess is that it should help with performance on full SSD drives and when there's a lot of small writes that burn through the pooled erased blocks.

I think it does; while theoretically the storage driver should maintain adequate empty blocks, often they don't - see reports of "SSD performance degradation".

FeFETs are planned for embedded non-volatile memory, eg. the memory for code storage build into microcontrollers, not SSDs. In current devices this is typically NOR flash, and the code executes directly from it. There's no pool of empty blocks, but the cells are single level so endurance is still acceptable.

The FTL (a sort of mini log structured file system that runs inside your SSD), works very hard to try to smooth over flash's erase block requirements. That said, it's far from a panacea, and many applications would be much simpler if they could just do real random writes to the physical medium.

Take a look at https://www.usenix.org/system/files/conference/inflow14/infl... for a nice summary of what issues pop up even for applications that make all their writes sequential.

There's another micro-optimization in play here: tipically, writing here is understood as the process of turning a 1 to a 0 (flash cells actually reset to a "1" value), and that transition is called "programming". If a write can be accomplished solely by programming, then it can be done in place, without having to reset the block or find an empty (filled with 1s) block to program the write to it.

"First and foremost, FMC is aiming at the embedded NVM space."

It also seems that they compare it with NOR and not with NAND, which again points to the scenarios where not much is stored and not often rewritten. Then it's not a technology for SSD's or USB sticks, how I understand it, but it's to allow to have a single chip which has both the logic and the re-writable firmware. And they claim it's cheaper to achieve that than with the competing technologies.

This stuff is fascinating, especially the challenges in fabrication as the theoretical limits are approached. I do have a question, if an expert could help explain. The article says,

"With FMC’s proprietary hafnium oxide, the standard gate dielectric can be made ferroelectric—even for film thicknesses that compare to the one used in standard logic transistors. This proprietary hafnium oxide integrates extremely well with all current and future processes utilizing HKMG. Therefore, a scalable ferroelectric FET finally becomes possible."

What is proprietary about the hafnium oxide? Is it the process of creating it, or the molecule itself?

Hafnium oxide itself doesn't seem to be proprietary, and neither does the process of producing thin films that have ferroelectric properties[1]. My guess is that they've made some additional modifications to the compound and/or process.

I'm venturing way outside of my field here, so I could be completely wrong.

[1]: http://aip.scitation.org/doi/abs/10.1063/1.3634052 (search for the title in Google Scholar to get a PDF)

If I understand it correctly, it is the process of depositing the HfO2 onto the wafer in a way that it retains its ferroelectric properties and is compatible with other chipmaking processes that is proprietary. Depositing it improperly would result in defects at the junction between the HfO2 and the underlying gate that would render the FeFET nonfunctional.

When I was in semiconductor manufacturing, we tried using a hafnium oxide layer in the capacitor dielectric for our DRAM. It did not go well, if I recall correctly (10 years back). Not for design reasons -- we were using it for its dielectric properties, not its ferromagnetic ones -- but for process reasons. It was hell on the diffusion furnaces. Flakes everywhere, wafers sticking. Lots of angry morning meetings.

A bit about Hafnium Oxide

http://semiengineering.com/many-paths-to-hafnium-oxide/

Sounds like an improvement over FRAM, which is already a shipping product that you can buy today - albeit more expensive than Flash and not as dense.

The ability to build with standard HKMG (high-k metal gate) wafer processing (unlike Flash) is very handy - means FeFET memory can be incorporated into high-speed microcontrollers.

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