Who is this author? This seems mostly wrong to me. Shrinking die size doesn't seem to have anything to do with the removal of tristate buffers from FPGAs. FPGA vendors are constently trying to shorten the length/amount of interconnects because it translates into faster designs with more logic regardless of die size.

What what I've heard/read. The RAM change is entirely due to architectural improvements and a shift towards "columnar" design. Architects have learned that having your data flow in a similar direction simplifies routing and leads to more dense and faster designs.

The pattern:

LOGIC <- CONTROLLER <=> RAM

Doesn't translate well to modern FPGA architectures because of the multiple data directions, so architects switched to:

INPUT/CONTROLLER -> RAM -> READ_LOGIC

* This is a simplification as FPGAs place and route is a pretty huge problem with many trades offs to consider.