The problem is that reset logic requires a bit of design rather than hard fast rules.

Designs are getting larger these days with a lot of 3rd party IP that you can't assume use a particular reset method.

Tips #2 and #5 in this article, http://www.eetimes.com/document.asp?doc_id=1278998 , explain how you have to tailor your reset methods to the modules you are integrating.

If you don't, you chew up resources.

A new FPGA designer should learn the first principles so they can understand how to make decisions and where to look for potential issues when bugs occur.