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Comment by wyager | Hacker News Reader

A bit late to the party, but my advice: unlesss your goal is to learn high-performance design, try to save yourself a lot of effort by using a higher-level HDL. Depending on how cool your professor is and what their pedagogical goals are, they'll be fine with it. Using something like CLaSH will statically prevent you from doing a lot of hardware stuff that's non-synthesizable, flammable, or just plain dumb. You can do a lot of things in standard HDLs that just don't make any sense, and a lot of students get confused and do them. Not only will something like CLaSH or Chisel prevent you from doing dumb things, but they will get you in the mindset of doing things correctly.

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I don't agree teaching students experimental high-level languages in lieu of proven industry standards just because those standards are archaic and/or un-intuitive. It's a great academic endeavor but the FPGA (and ASIC) landscape is driven by industry not by academia.

If you're aiming for an FPGA job after school you'll need to be proficient in verilog or vhdl (ideally both), there's no shortcut. The sooner you learn how to deal with their quirks and pitfalls (I agree they have a lot), the better. Sprinkle some good-ol' TCL in there and you're good to go. Yes python is better and more feature/library rich but the industry is still using TCL (which is not bad, just not modern).

Don't get me wrong, I'd like to see a standardized higher level approach to hardware description, but unless the vendors agree and support it there's very little chance it will be useful. The current trend in high level synthesis is non-portable vendor specific tools. The only way I see the trend changing is when FPGAs become more mainstream (already happening in the server/deep learning sectors) and there's a critical mass of customers that ask for FPGA tools in par with software tools (ie. high level languages, open source, etc.)

PS. You forgot the python based myHDL :)

Using high quality modern HDLs helped me to understand how e.g. Verilog should be used more than using Verilog ever did.

It's the experimental part of the high level language that is the problem. I agree you shouldn't teach it to students. It just leads them down a divergent path away from what is done in industry. It isn't addressing the needs of the student, only their short term "wants".

But the language is just a small part of the design process. You have to be learn to design HW. The HW engineering project tailors the tool choices around the requirements of the product. It is assumed that engineers know the fundamentals. They can adapt to any high level synthesis tool.

Vendors training courses for all fancy HLS tools are done in a few days at most. They don't have a semester for any newbies to learn Verilog/VHDL or C/C++ first. It's assumed you know them.

Meh. Anything that tries to fool beginners into thinking they're writing software rather than defining hardware is a bad idea.

Understanding why something is non-synthesizable or inefficient in hardware is 90% of your education as a chip designer. Exposure to HLS tools can, and should, wait.

Neither CLaSH nor Chisel do this. You're probably thinking of stuff like SystemC, which attempts to compile C-like imperative code to hardware.

If your language (in the case of CLaSH) or DSL (in the case of Chisel) is designed correctly, there's a clear and direct correspondence between high-level semantic constructs and low-level hardware constructs.

Take a look at Conal Elliot's Lambda-CCC. The semantics of synthesizable hardware and the semantics of lazy lambda calculus are exactly the same in many fundamental ways. There's no fooling or trickery going on. If you understand why your lambda calculus program is divergent, you understand why your circuit is unstable.

2nd. There's also Lava (and variations). Lava predates both CLaSH and Chisel.

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