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Apart from the fact that the cache needs to be invalidated before/after a DMA transfer to ensure cache coherency (automatically or not, depends on platform), DMA allocations have no problem with caches.

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DMA allocations have no problems with caches, but in some situations you can get a performance boost by marking as write-combined if the CPU only writes to the memory once and then hands it off. This results in less cache being occupied with useless data and can be beneficial due to coalesced writes, but will result in horrifically slow CPU reads from the region.

I am suggesting that the author conflated "DMA allocation" with "write-combined allocation".

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