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Comment by dboreham | Hacker News Reader

Lack of silk screen doesn't have to be an obfuscation measure : silk screen is an extra process step during PCB manufacture and if you don't need it, omitting the step saves money.

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Exactly. The test points don't need to be numbered either. The CAD tool they use to design the boards can produce a bed-of-nails pattern that can be fed back into QA testing machines. If something fails, they can pinpoint it through the testing facilities and propagate the failures up the chain. At least in my experience with modern manufacturing, unless you have someone doing manual testing with a spring-nail, labelling the test points is completely optional.

Do you know the term for the QA setup/device to test multiple PCBs at once? Or to e.g. write firmware to more then one more at once? What are some search terms for that?

e-testing? usually each board/manufacturing house has its own in house custom solution.

btw nice trick for vscored panels to avoid huge number of test points https://www.youtube.com/watch?v=V5BDcEqEaKg

Yeah I didn't realize that there would be a lot of one-off in-house methods. Besides board/panel level strategies, I was curious physically what kinds of rigs or harnesses are out there, if there were any industry standard setups. But maybe it's doing smart things at the panel level and building custom testing rigs in house.

That's done while the boards are already populated, but not de-panelized yet. All boards in the panel are connected to the JTAG bus, that connection will be broken when you remove them from the panel. JTAG traces run in the "frame" of the panel. So you have a single connector on a panel that you use for flashing firmware and doing boundary testing. Dave Jones @eevblog explains that in one of his videos. I can't remember which one, but I'd start search from this series https://www.youtube.com/watch?v=VXE_dh38HjU

Thanks for the guidance. His design for manufacturing series will be good for me to go through.

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