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Comment by sanxiyn | Hacker News Reader

> No announced RISC-V silicon is susceptible, and the popular open-source RISC-V Rocket processor is unaffected as it does not perform memory accesses speculatively.

True but misleading. Rocket is an in-order chip. Not only it does not perform memory accesses speculatively, it does not speculate at all.

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Presumably an in-order chip is slower than the sophisticated modern out-of-order processors around nowadays and faces marketing headwinds accorindgly. It's only fair to gain a marketing tailwind from the problmes caused by aggrssive speculation.

Rocket has a branch predictor; if you're not going to do any kind of speculation, why have it in the first place?

AFAIK its load store unit does plenty speculation.

Preloading instructions into the cache or only executing instructions speculatively which only modify the CPU's internal state and no caches.

a pipeline flush and unprefetched instruction fetch on each branch (20-25% of insns) would dramatically slow down the CPU. With branch prediction you can potentially have correctly predicted branches take zero cycles, even without speculative execution.

Using a branch predictor to start execution of a branch is speculative execution.

In established computer architecture terminology, speculative execution is reserved for speculating past branches. (Speculation meaning something that may not pan out...)

This shouldn’t be downvoted. The reason to have a branch predictor is so you can speculatively execute down the predicted path when you hit a branch. Although I think the Spectre attack requires not only speculation, but the ability to perform loads out of program order.

It's a reason, but not the only reason. In-order superscalar processors rely heavily on branch prediction too.

The direction of a branch isn't going to be known until a couple stages into the pipeline ("EX" in the classic RISC version). Ideally, the preceding stages in the pipeline will be fed correctly - that can either be the instructions immediately following the branch (as in the "branch delay slot(s)" found in some architectures) or the instructions at where the CPU thinks the branch will lead.

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