Hey folks, I'm the owner of the Intrinsics Guide at Intel. Let me know if you have any specific feedback or questions you have.
Since version 3.3.16, including the current 3.4, the guide no longer contains this info.
Why have you removed that?
Otherwise, this is one of the best cpu documentation tools I've used.
As a side request, it would be amazing if the intel documentation on non-temporal memory operations and sfence+lfence had more specifics about how they interact with the rest of the cache hierarchy and the load/store subsystems.