It's really godawful. Software guys have no idea how good they have it.
You have layers upon layers of closed source EDA tools and home-brew scripts, all built around horribly abysmal "standards" like SystemVerilog, mostly cobbled together in TCL and Perl.
For instance, the following sounds like a horrible joke, but it is real. In a real life, world-class company, port connections between modules are handled using a Perl script. This perl script invokes, I shit you not, an Emacs-Lisp Verilog parser, that scans your files to figure out what submodules you are instantiating, infers the ports that you want to connect, then injects a blob of connections directly into the source code file you were editing. The engineers at this company then commit the output of this Perl script into their source code repository. Predictably the diffs are full of line noise.
And you can't escape from this, any of it, because there are so many tools involved, and they all do such useful things, that you end up truly stuck using whatever features all of the tools support. And `ifdefs. Sigh...