SiFive to release source code to initialize HiFive Unleashed RISC-V board
forums.sifive.com
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HW video decoding, display protocol driving, 3D, ... Is there any open hw initiative on that front that I'm not aware of ?
And does it have real-time support?
First off there is an Intel SMM-like layer (M mode) running under the operating system. Unlike Intel it's all open source. So if you find that something in M mode is taking too long and disturbing your real time guarantees, you at least have a hope of fixing it.
Obviously Linux is no use for hard real time, but in the HiFive Unleashed board there is a separate RV32 core on the side which actually does nothing except spinning in M mode. It literally runs this loop:
https://github.com/riscv/riscv-pk/blob/600ff370c65ba99d2103a...
You could have this spare core do anything you want while running Linux on the application cores. I believe it has full access to RAM and GPIO pins.
Secondly there is a 96Boards compatible expansion header with some but not very many GPIO pins, see section 8.2 here:
https://static.dev.sifive.com/HiFive-Unleashed-Getting-Start...
Thirdly the clock currently runs at a constant speed (but settable), so there's no power management, both a good and a bad thing, but probably good for real-time.
While it's true that the mainline kernel is not currently capable of delivering hard real-time performance the PREEMPT_RT developers keep chipping away at the remaining issues. LinuxCNC users have been achieving hard real-time performance on their controls through the use of the PREEMPT_RT patches for some time now.
It's a 999$ development board, so no. Hopefully RISC-V based hardware will get to mass production at some point, but that's in the future.
lowRISC was founded by:
Robert Mullins - Computer Laboratory, University of Cambridge, co-founder of Raspberry Pi
Gavin Ferris - Dreamworks, Radioscape (co-founder), Aspect Capital (former CIO)
Alex Bradbury - Computer Laboratory, University of Cambridge and Raspberry Pi
They are promising a completely open design. But to achieve that without proprietary IP blocks involves using so-called "minion cores" to handle I/O, where a minion core is a cut down RV32 core hanging off the side of the main RV64 application cores. The minion cores would essentially handle I/O by bitbanging, which sounds OK for slow devices like serial lines and perhaps even fast ethernet, but I'm not sure how well that's going to work for SATA, gigabit ethernet or DDR4 RAM.
Both Green Arrays [1] and Xmos [2] have a similar arch when it comes to IO.
One thing I forgot to say about minion cores is that they could be used to control external chips. For example if you had an external gigabit ethernet device which could do DMA then the minion core would only have to bitbang the control plane (per packet), which seems much more achievable.
Of course this just moves the proprietary IP outside the SoC into an external IC - I don't know if that's a good or a bad thing in itself.
I am envisioning something like AVX (grid of registers) for running state machines with built in SERDES (parallel loads/store, serial in/out) for running IO.
Their IDE is Eclipse based (or used to be), though the language used is a variant of C. I still have 2x their original audio dev boards here. They have ports galore on them (USB to PC, then 7.1 channel out, 7.1 channel in, SPDIF, has it's own timing crystal, and apparently does things well at 192kHz). Could have sworn they do 384kHz as well, but that doesn't seem to show up in any of the options (when I last checked anyway).
These days mine are just getting used as weird looking consumer items. eg to drive the 5.1 setup on my CentOS 7 desktop. ;)