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Comment by whatever1 | Hacker News Reader

Bloody hell, this processor has more cores than the dual socket Xeon HPCs that my lab bought 2 years ago. Amazing. Honest question: Isn't the memory throughput an issue when you try to feed 32 hungry processors?

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Threadripper uses quad-channel DDR4-2666 memory. That gets you 80 GB/s memory bandwidth, which is possible because the processor sits in an enormous 4094-pin TR4 socket. Your Xeons were probably in 2011 pin sockets with DDR3-1866 resulting in 70 GB/s memory bandwidth. One Threadripper has more than double the pin count and slightly more total memory bandwidth than your dual Xeon machine.

Also, your the Intel setup has a 25 GB/s QPI bus between the processors. Threadripper runs an Infinity Fabric bus, with 42 GB/s between each die internally (aggregate 170 GB/s). While a couple of those internal dies are not directly connected to the memory, you should have little trouble sharing meals among those hungry processors.

Actually with this release threadripper 2 will support DDR4-2933 which should increase the memory bandwith and the throughput of the infinity fabric if I'm not mistaken (I am pretty sure infinity fabric runs at the ram speed)

Most people overclock RAM using XMP settings and hit 3200 MT/s easily (which also overclocks the infinity fabric).

I've seen some people hit 3466MT/s on higher-end more expensive RAM on AMD's 12nm stuffs (Ryzen 2). So that's probably the practical limit.

3200 MT/s on Hynix dies is probably a reasonable expectation.

Do you know whether Threadripper is affected by NUMA issues? Otherwise this could be an additional selling point for applications that need a lot of memory (e.g. databases, where you do not want the memory latency to be unpredictable depending upon which socket you are running on)

It is. Only 1/2 of the dies are connected directly to memory controllers.

For actual production workloads you want EPYC which has a memory controller for each die, meaning it's 8 channel.

Depends on the arithmetic intensity. Higher intensity means less memory bandwidth needed to keep the cores happily crunching.

> enormous 4094-pin TR4 socket

A lot of these pins aren't used on TR, since you only get half the memory controllers you'd have with EPYC

That's true. A staggering number of them are power delivery to start with - you don't waste anywhere near half the socket by dropping 4 memory controllers (!) but yeah, it's not EPYC.

For what it's worth, Broadwell E5v4 Xeons (which have been out a little over 2 years) use a 2011-3 socket and support DDR4-2400.

Well, it's got four fairly fast memory channels but yes, you'll probably tend to be more memory limited with this guy - though the 64 MB of L3 should help in many cases.

For TR kind of. In the newer models only half the cores have direct access to a DDR channel. This shows in memory bounded benchmarks, but Epyc (server line) elevates this problem by have 8 (!!) memory channels, instead of the consumer TR’s 4.

Ultimately it depends on how cache friendly your workload is.

The 32c/64t is kind of a marketting gimmick selling binned Eypcs. If your doing memory bound HPC consider the 16c/32t model for roughly equal performance at a lower price.

Do we know if the 16c TR (2950x) will be full bandwidth or not? I'm assuming it'll still be halved due to die count/arrangement?

2950X is using two dies with 2 memory channels each, basically an update of the original Threadripper with Zen+ dies.

That's what I was hoping to hear. Thanks!

EPYC fixes the problem by having 8 channels. All cores have direct access to DDR.

It's the unfortunate downside to these. Two of the dies don't have direct access to memory, but it seems like AMD didn't want to do a refresh of the pinouts and force socket updates. I suspect this will be left for the Zen 2 version of Threadripper. That being said, I imagine in most circumstances the performance should still be pretty good.

Yes, hopefully the motherboard manufactures take that seriously.

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