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Comment by bogomipz | Hacker News Reader

The author states:

>"It is indeed a healthy design paradigm to stick to synchronous circuits in general, if possible. Then, quite obviously, all elements of a circuit operate concurrently, literally at the same time. Every variable and register is defined by one and only one expression combinational circuit). Multiple assignments do not make sense."

I am not quite grokking this and hope someone can explain this to me.

He starts by extolling the merits of sequential logic circuits but then goes on to say that every variable and register need only be a combinatorial circuits. Since these are the two fundamental circuit types, does this point not contradict the earlier one? What am I missing?

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Reading further: "In order to simplify an explanation, we restrict our analysis to synchronous circuits — that is, circuits in which all registers tick with the same clock"

Sounds like the author is advocating for designs that do not have derived clocks or gated clocks or multiple clock domains -- all tricky things that designers occasionally do with great care. Clock your flip-flops with the master clock and avoid transparent latches and your design will approach the mathematical ideal that he describes when comparing a circuit to a software program.

I'd guess his Lola HDL restricts you from doing some of these things, where Verilog is more YOLO depending on the vendor and warnings that are enabled.

He said "synchronous" (synchronized by a clock), not "sequential."

"Synchronous" is a type of sequential circuit. The "synchrony" or sequencing is derived from the clock signal.

https://en.wikipedia.org/wiki/Sequential_logic

Yes, you're right of course.

Looking at it again, I'm reading Wirth's statement as pretty much a bog-standard endorsement of synchronous circuit design.

Yeah it's the "Every variable and register is defined by one and only one expression combinational circuit)" part that confuses me, since he seems to use that to support the endorsement of synchronous design. But maybe I'm just reading it wrong though.

Channeling my inner Wirth, I think he's just saying that, for the duration of any given clock cycle, synchronization ensures that every combinational building-block within the sequential circuit will have a consistent state.

There are two parts to a synchronous design - the combinatorial bits, and the flip-flops.

  /----\    |-----|
 /      \   |    Q|
 | COMB |---|D    |
 \      /   |>CLK |
  \----/    |-----|

I think what he's getting at is that any combinational logic that goes in a register is defined in one place - he's not doing complex statements.

It sounds like he's doing a very (terse) RTL style. This makes it very clear what your synthesizer will do with it - he isn't trying to be clever on the RTL front.

We should email him and ask!

Thanks for channeling your "inner Wirth" :)

Also thanks for the ascii diagram.

In re-reading that passage this all makes good sense now.

Cheers.

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