There realy should be some kind of ISO about node naming.
I guarantee this "5nm" would be as much missleading as their "7nm".
Only thing that matters is wafer price, yield, transistor count and TDP.
But when we hit 20/18/16/14nm that went out the window and it became a marketing term, not so much a literal description. A lot of this was driven by moving to FINfet's which are really MOSfets, as they have lower leakage at smaller sizes, but they also aren't square which makes generalizing a singular node to density a bit wonky.
Size is small enough for anything consumers care about, even watches.
Wouldn't 5 nm allow shorter wire traces, which would reduce another limiting factor in computational speed?
The fundamental limit of clock speed is power draw. As clocks increase the wattage ~ frequency relation goes from
frequency = Constant * Power Draw
frequency = Power Draw * Power Draw
Packing things in more tightly lets you spend less time in transit, which might let you squeeze more gates into a cycle, or do the same things a little faster.