AMD’s Rome is indeed a monster
semiaccurate.com
semiaccurate.com
That said, this really does look like a pretty awesome chip for data centers. I would love a dual socket mother board that had 512G of RAM 1TB of Optane memory as additional "RAM", then 16TB of NVME SSD storage, and 32 SAS/SATA channels for an effective 360TB of rotating disk (dual parity RAID 6, 30 active drives, 2 parity drives). And then make a cluster of 48 of those monsters.
Ah the places we would go and the things we would do with such a system.
For a large write-heavy setup + "we will restore from yesterday's backup" mode of operation, you may likely be better off with a RAID10 which is faster. (Though RAID50 and even RAID60 are a thing.)
I've used dual parity RAID systems for over a decade now and they work superbly when rebuilding even during a drive failure. (aka in 'degraded' mode). I typically run them in 22 drive sets because that is how many drives fit on a single NetApp drive shelf.
The age of the company in a case like this is irrelevant. What matters is current management and staff and market context.
With less success then
AMD didn't squirrel away the advantage. Intel abused their monopoly to starve out AMD by giving OEMs discounts if they agreed not to carry AMD chips. They paid a paltry 1.5B in fines for abusing their market dominance.
they didnt https://www.lexology.com/library/detail.aspx?g=8965e7a2-ac87...
That isn't really what happened though. It was a combination of two things. One was this:
https://www.extremetech.com/computing/184323-intel-stuck-wit...
The other was that it happened around the time when CPU frequencies hit the power wall. That hit the Pentium 4 especially hard, which gave AMD the advantage, but Intel's anti-competitive behavior prevented AMD from capitalizing on it. Meanwhile Intel knew the Pentium 4 was too power hungry for laptops, so they kept iterating on the Pentium M, which is what became Core. It was designed for power efficiency rather than clock speed right when clock speeds unexpectedly started getting limited by power. It wasn't expected to be faster than the Pentium 4 (at half the power), but it was, so Netburst got canceled and suddenly Intel had the advantage.
The combination of the two things meant that AMD never had a chance to really profit from its investment in Sledgehammer, which meant they didn't have the money to put into R&D and fell behind for a decade.
There is no guarantee something else won't go wrong, but the chance of that same confluence of factors happening again seems pretty unlikely.
Working with a $399 threadripper motherboard that has four x16 physical slots, it can accommodate four Intel x710-4 10GbE four port NICs (each electrically x8), for a total of sixteen 10GbE router interfaces in a Linux kernel based FRR system, as a fully software implemented router. And with the RAM capacity of a 32GB system, no worries about FIB size. It's a very different approach to do with a routing entirely in CPU vs ASICs. But this can be built for under $4000.
Or one could just as easily use those four physical x16 slots for four independent 100GbE interfaces.
I suspect there might never be one so as not to muddy the waters of Epyc's intended market.
I don't have any dog in this fight, SA is just a terrible news source.
How do you know?
Yes and does not belong to HN.
But reading between the lines, AMD is only showing benchmarks for extremely parallel loads much like they did with ThreadRipper 2. Between the physically separate processing cores and the nature of the marketing benchmarks, I suspect workloads that have high IPC or extremely low latency requirements won't fare so well on this chip.
The weirdest part is to think what Apple might come up with if they were to take the A12X design and connect it on a die like AMD has done here. It would probably make for a pretty interesting Mac Pro.
However the strategy to go with gluing smaller dies together also better fits the (long known) pragmatics of manufacturing processes. This allows AMD to hit lower price points and while getting better margins. It also coincides with Intel being hit with "The Thermocline of Truth" where they were too optimistic about overcoming the challenges of larger die sizes.
"The Thermocline of Truth"
http://brucefwebster.com/2008/04/15/the-wetware-crisis-the-t...
Now with 64 cores in one socket things got even weirder, but then again, those licenses always have been in some parallel universe.
PS: I have no affiliation with velocity micro, have never bought from them
A TDP of 90W is about the limit for CPUs using cheap cooling techniques, and adding ram would lower that by 10-30W.
To mix the two for thermal reasons would lead to some crazy multi-chip modules as in the "chiplet" approach reported recently. However, I suspect you would need far too many chiplets and too many bonds to really give you this thermal benefit rather than just having individual chiplets which are still hot spots with problematic cooling.
I keep reading that some data centers switch to liquid cooling, so likely it does. Maybe with advances on this front, we'll see the increase of the CPU efficiency that the fabrication process can no more deliver.
Imagine you have a cache miss on literally every memory access and have to pay a 100 nano second penalty to access main memory. SMT allows the CPU to switch to a different thread during a cache miss. Effectively you can have 128 memory loads at any given time. 100ns amortized over 128 threads is less than 1 nano second. Since the minimum size you can read is a 64 byte cache line this means that program will require at least 64GB/s of memory bandwidth even though your CPU is stuck on cache misses.
Of course if you thrash your cache on a modern general purpose CPU, you're going to have a really bad time. Pretty much if you're getting close to worse case memory access like in your example, you need to step back and re evaluate quite a few of your choices.
It might make more sense now that there are more types of memory-like storage which isn't quite as fast as DDR4, like Optane.
There is also an infinitely more tricky issue: security.
Network requirements: https://www.usenix.org/conference/osdi16/technical-sessions/...
Two systems that use remote memory: https://www.usenix.org/conference/nsdi17/technical-sessions/... https://www.usenix.org/conference/osdi18/presentation/shan
Additionally DRAM more or less has to be separate chips due to the sheer surface area for yield reasons. The amount of DRAM in a decent sized server is close to a whole wafer.
https://en.wikipedia.org/wiki/Meltdown_(security_vulnerabili...
The other big box to check is Spectre mitigations are now rolled in to the core but Meltdown and L1TF/Foreshadow are not. Why? Because AMD wasn’t affected by either one and never will be. Patching can work but to be immune from the start is always a better choice.
Btw, zen 2 will take the lead at every metrics.
Looking at fastest single-threaded CPUs:
https://www.cpubenchmark.net/singleThread.html
The fastest Zen+ is 2950x at position 85, roughly as fast as Broadwell C, with score of 2230. Now 13% more would give it 2520, roughly matching Haswell 4790k (number 15).
So no, it's not likely going to lead every single metrics.
7nm will allow higher frequencies too which should make the difference. If Intel still lead in single thread it would probably be negligible.
Either way, Zen chips are already multi die chips. For Zen and Zen+ each die has (up to) four cores. Chips with more cores than four contain multiple dies.
For Zen 2 they are going to be mixed differently, which is what you are referring to.
Each wafer, which is the disk on which many dies are produced, is produced using a single technology process. This means that Rome's IO dies (14nm process) are produced on separate wafers from the core dies (7nm process). The wafers are sliced into dies, the dies are tested and binned separately, and sufficiently good dies are then packaged together into a single package that goes into your server's CPU socket.
The wavelength of the laser used for the manufacturing is a different story entirely. Pretty much all state-of-the-art photolithography uses 193nm wavelength lasers, and this has been the case for many years. Yes, the wavelength is larger than the size of the features produced with those lasers. There's a lot of magic involved.
Since it's getting a bit too much magic, the industry has been trying to upgrade to 13.5nm (extreme ultraviolet) lasers for a long time. They're now starting to be used in actual practice. And EUV lasers are still basically magic, but of a different kind.