Open Source IDE for FPGAs as QtCreator Learns Verilog | Hacker News Reader

Open Source IDE for FPGAs as QtCreator Learns Verilog

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81 pointskungfudoi20 comments

I don't do FPGA, but I thought the issue was the vendor lock in and lack of open source tooling (Synthesis?) rather than IDEs alone?

Now that there's some open-source synthesis tooling for iCE40 it's nice to have a fully open solution, even if it does really only address the needs of the open-source diehard and entry-level hobbyist. Without an IDE it's harder for open-source toolchains to gain momentum so anything helps.

That's still the case, but open-source tools are useful for simulation, and there are synthesis tools for the Lattice iCE40 family: http://www.clifford.at/icestorm/

There's the symbiflow umbrella project that subsumes icestorm. In addition to ice40, they have apparently a working synthesis toolchain for lattice ecp5, and are working on supporting xilinx series 7.

https://symbiflow.github.io/

That being said, AFAIU newer generation fpgas from xilinx and Intel have encrypted bitstreams, foiling reverse engineering attempts. One can hope that the emergence of an open source synthesis toolchain would encourage new entrants by lowering the entry barrier.

FOSS simulators are almost totally useless; they can't handle mixed languages, they can't work with encrypted RTL (found in various Xilinx IP), and ones like Verilator are cycle simulators that don't even handle testbench code.

There's a very, very narrow niche where FOSS simulations are useful, and I'd wholly recommend against wasting your time with them.

Lots of people use Verilator in production, as far as I can tell.

But sure, if your upstream tooling produces DRM blobs instead of actual RTL, then your software has to implement those DRM mechanisms to use it; but that's more to do with your specific industry than with anything else.

Your hyperbole is already confusing newcomers, I'd dial it back a bit.

I don't know that it's hyperbole - Verilator is a huge leap for a newcomer. We're going to take someone who is just getting into Verilog, and add C/C++, makefiles, then we're going to add the problems you've got with a cycle simulator (testbench code won't work) - we have to explain what a delta cycle is, and the most popular tutorials online (ZipCPU's Verilator blogs) mention using a delta-cycle simulator (like Icarus) just to check that you're getting what you expect.

It's frustrating that people keep suggesting FOSS tools when they're either orders of magnitude more complex, not very good in a huge number of cases, require an experienced engineer to actually use, and can't simulate simple Xilinx IP.

People think they're familiar with it because they looked up "FOSS Verilog Simulator" once because they were curious, but they can't actually tell you about these things. We should direct newcomers to Xilinx Vivado, getting started with ISim, and if they're far more sophisticated and have a handle on the language already, then move them to Verilator in certain cases.

But starting with Verilator would be like saying, "Just write a C compiler in assembly, then start using that C compiler." - Nobody starts there!

The first time I tried to set up Xilinx Vivado, Xilinx swallowed my license and didn't provide a board definition for my Zynq (for which the license applied); when I tried contacting them, they couldn't help me work it out.

Maybe it's possible to direct newcomers to Xilinx Vivado, and I agree that they're more likely to be productive that way, but there's also a good chance their investment will go up in smoke and they will have no way to debug that. It's not as though the thing is "easier" in every way than using any of the public simulation tools, and it sure as hell costs more when it goes wrong.

Board definition files don't do a license check, only bitstream generation does - so it wasn't a license issue. But let's examine this more closely:

https://www.xilinx.com/products/design-tools/vivado/vivado-w...

The largest supported Zynq-7000 with the (free) Webpack is the XC7Z030.

The $900 ZC702 has a XC7Z020 on it, which is a Webpack part (no part license needed), so you probably bought the $2500 ZC706 (which contains a XC7Z045 part)?

So you bought a ~$2500 board, and the license was successfully applied, but you couldn't get the board definition file to work (a part that has no license checks...) now you're claiming that the investment would be "up in smoke" for a newcomer?

Honestly this sounds like user error; Create New Project -> Enter name and location of Project -> Type of Project (Select RTL, fine) -> Click on BOARDS and select your board -> Finish.

Now when you use something like IP Integrator, the board presets should be available. If you're still having trouble with it, I can walk you through it with screenshots if you'd like, but there are also tutorials and videos from Xilinx that go over "Creating your first project", they're a great way to get started; try this: ZC706 Getting Started Guide (includes screenshots of not only the hardware, but every step):

https://www.xilinx.com/support/documentation/boards_and_kits...

I use Icarus Verilog at work for a fairly complex trading system on an FPGA so I disagree that FOSS simulators are almost totally useless. It supports most System Verilog features and works well with cocotb. In fact the fact that it’s open source also allows me not to have to worry about license usage (which has always been a problem using modelsim). I managed quite well abstracting the Xilinx is (most up like rams can be inferred in the code) and things like pcie, transceivers, ddr4 have well defined interfaces so are easy to model in straight Verilog

You use Icarus for a trading system - exclusively, or when you can't get a license checkout for something better?

I can't imagine a FinTech shop wouldn't have access to MSim (or Questa).

I use it exclusively. I know of other trading firms that use verilator too. To be honest, no matter how big the company, how deep the pockets, theres still going to be a finite amount of questa licenses available. If you use Icarus Verilog it allows you to farm out simulations to anywhere, run as many in parallel, which would not be possible with questa (as you would eventually run out of licenses). Also, I think icarus verilog actually works pretty well, it covers enough of the system verilog syntax to be useful for RTL and with cocotb I don't need access to the system verilog testbench stuff.

I use Verilator to run simulations in the browser, which is useful to people who want to learn Verilog without installing anything: http://8bitworkshop.com/blog/release/2018/12/15/verilog-prog...

They're learning a subset of Verilog which excludes test benches, which is a huge amount of a project (by code and by time) and is introduced in every single beginner HDL text.

You'll probably be in Chapter 3 of most books when this simulator fails you in a way you can't figure out; I think this is pedagogically unsound to say it is good for newcomers. If they started with a low cost FPGA board and XSim, they could practically use everything they'd learned.

Are there any simulators that would be good for entry level "I want to learn verilog from no understanding of electronics"?

Sure, get the Vivado Webpack (which is free as in beer, but not as in Freedom) and use the built in simulator, XSim.

It's multi-language, handles encrypted Xilinx IP blocks, and is more than enough. As a side benefit you'll be getting familiar with Vivado, which is broadly used in industry.

It's not "Free as in Freedom!" but it's actually useful.

Thanks! I'll check that out!

Sorry, the example image is using non-blocking statements. I'm out.

On a more serious note, I'm not sure what this offers me beyond the SystemVerilog plugin for sublime-text. This may be a great tool for exclusively open source developers, but in reality I think most people are using free versions of proprietary tools (Quartus, ISE) and you can't really do much integration with those.

= are blocking assignments, and they’re what you’re supposed to use in a combinatorial always block. Are you thinking of non-blocking <= used to assign to a dff?

It's an IDE, not a compiler or synthesis tool - it replaces your editor and make files, not the tools that actually process the language

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