I've been designing semiconductors for 23 years. This article is 17 years old and I haven't seen any clockless designs in my professional experience in all of that time.

About 1/3 to 1/2 the power usage is leakage and I don't see how a clockless design will help that. We dynamically lower the voltage and have power islands for unused or lesser used portions.

nbingham makes a great point about the tools. We have invested billions of dollars in tool flows. We are not going to throw that away until we see some proof that clockless designs are better in some measurable ways.