The OpenROAD project on lowering ASIC costs and design times

This seems to be mostly an umbrella effort, focusing (according to their home page) on the "RTL to GDSII" part of EDA. To the extent that they're successful, it would be quite complementary with other efforts in open hardware design, focusing on generating RTL from very-high-level, parameterized, quasi-functional hardware descriptions. But I'm a bit skeptical about their overall goals, particularly since one key issue with modern ASIC design is the unwillingness on the part of fabs to openly share critically needed info about their design rules or other proprietary details of their design-related workflow - and there's no way that open-source software alone can resolve this. Of course I do think we can expect a few useful tools to come out of this effort, and maybe that's compelling enough.

This software is what Cadence will gladly charge you $1M/seat. Seems pretty ambitious to pull this off for free.

See their GitHub repositories: https://github.com/The-OpenROAD-Project

At first I was very confused what this had to do with the 4GL RAD language that been around since the early 90's. Seems like a poor choice of name for your project. https://en.wikipedia.org/wiki/OpenROAD

I see no code repo, no IRC/discord channel, etc.

Either this project is just a pipe dream of it isn't as open as its name implies.