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jhallenworld

It's missing the below 5 cents microcontrollers:

https://lcsc.com/product-detail/PADAUK_PADAUK-Tech-PMS150C_C...

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I looked through the datasheet, but couldn't figure out what "1KW" of program memory meant.

Looks to be a typo for 1 KiB, since the address space seems to go from 0x0 to 0x3FF.

1 thousand words, probably.

It's supposed to be 1kW, ie 1024 words.

A 1,000 cpu cluster for $29. Nice.

A MCU is sadly not a CPU, for example, most use the harvard architecture, meaning code memory is in ROM and uses a separate address space than data, which usually lives in SRAM. This limits a lot of things you could possibly do. RAM is also very very limited and you have to use it for any data you put on the stack as well as on the heap. You could however, emulate a very very weak and simple CPU on it.

I think it's a stretch to say "most [MCUs] use the harvard architecture, meaning code memory is in ROM and uses a separate address space than data" since I have not encountered so far not even one device (in the about a dozen or so that I worked with in real life) that actually had a different address space for RAM than ROM.

I will say that for the particular one that OP linked above, this does seem the case since the datasheet mentions "ll the 64 bytes data memory of PMS150C can be accessed by indirect access mechanism."

Your compiler or assembler might abstract it for you but most (basically anything smaller than an ARM Cortex-M) will have harvard architecture. Some MCU's ran run programs from RAM but IIRC they do it by loading RAM into Code Memory and then executing it, it looks like VN from the outside but isn't quite on the inside.

Harvard doesn't specify if you need an indirect access mechanism, plenty of HV computers can access their code memory fairly normally (either by using a special bit in the bus or opcode or mapping it into a unused section of normal address space). Harvard simply means that Code and Data come from a separate bus and in most cases that means separate devices.

If your MCU has two seperate specs for Flash/EEPROM as Data and Program Memory, then it's 100% Harvard. And that's basically most of them.

I am not arguing about the existence of Hardvard arch. on MCU's but rather on the fact that most of the time, RAM and ROM memory accesses happen in the same address space. For sure, the underlying HW might connect you to different buses, but on a lot of MCU's, from the programmer's perspective, the address space is a big flat area containing everything.

For sure, my experience has probably tainted my outlook. I have the most experience with Renesas MCU's and for example on them, I can surely run programs straight from the RAM, and depending what you're doing, you might sometimes be forced to do so. I worked with Cortex M also, and they're flat address space too.

I did check out the specs for Atmega MCU's and it seems those, as you described have different address spaces for data and code areas. What I want to say, I guess is that you can have a huge variety of options and architectural approaches for MCU's.

How is the documentation on those?

Not great, Dave from EEVblog did a few videos on them and how to use them. I think they're all OTP

https://www.youtube.com/watch?v=Rixo78hv_lw

OTP = One-time programmable

Fine if you can read Chinese.

There are several discussions about them at eevblog, with many people having success. It's probably the best place to get information in English.

The datasheet covers hardware + software (instruction encoding, I/O registers) and it's all in english here: https://datasheet.lcsc.com/szlcsc/PADAUK-Tech-PMS150C_C12912...

Surprisingly acceptable. The datasheets are reasonably legible and there's a weird but perfectly usable SDK. Padauk clearly don't care about the hobbyist market or more specialised applications that require certification or long-term availability, but their offering seems like an entirely reasonable choice for low-cost, mass-market products.

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