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Comment by bufferoverflow | Hacker News Reader

That's pretty wild. Most atoms are 0.1-0.2nm in diameter.

It is indeed pretty wild but the "3 nm" name is not an actual distance, it is a marketing term supposed to represent the transistor density. The actual transistors are much larger than that.

For example Intel's 10nm is equivalent Samsung's 7nm. They both have a pitch of around 40nm.

Any comparison for transistor density (and power consumption) of different manufactures/generations? Though probably they are hiding this as hard as possible, throwing only marketing nonsense on consumers.

At this point I don't think they physically measure anything on the chip to get that number. It's just an indication of how tightly you can space the transistors, plus a bit of marketing hype. The pics in the article make me wonder if the new gate design is even wider than before, but allows for stacking up transistors which ends up increasing the density to the equivalent of 3nm.

> At this point I don't think they physically measure anything on the chip to get that number.

They are measuring the smallest feature size - the smallest shape that is reliably replicated across the wafer. Actually pretty impressive when you think about the lithography behind it.

Not in this case. It's mostly just a marketing term. If I wanted to be pedantic, Intel's first gen 10nm has a tip fin width of 7nm. 14nm had a tip fin width of 8nm.

https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-...

Also critical, the crystal lattice spacing between atoms for silicon is 0.5nm

Kinda makes me wonder what the absolute limit is. Is a 3 atom transistor possible?

Going much smaller than we have right now, and you run up against some exotic issues--if you decrease the dielectric thickness, you run the risk of break down between the gate and source/drain under normal operating conditions. Your steady current rating also drops dramatically if the other feature sizes are decreased. I would probably say a 3 atom MOSFET is not possible, since at that scale you can't really have an effective dielectric between the atoms, and the conductors connected to the "single-atom terminals" will have a bulk effect on the behavior.

> if you decrease the dielectric thickness

This is why people are moving away from planar transistors to "FinFets" and eventually having an "all around gate"

https://en.wikipedia.org/wiki/Single-atom_transistor

3nm (or any "node" measurement) is not a measure of the entire transistor, only of the smallest feature size.

What do you mean by "feature size"?

A semiconductor is made of multiple surfaces/areas. Their lithographic process allows to have some at 3nm in size, but a transistor can be a sum of many parts.

A very rough approximation would be to describe a wind-up watch (processor) by the smallest tooth of the smallest gear (component of the transistor)

You can go pretty small: https://www.nature.com/articles/nnano.2012.21

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