Some variation of this gain is implemented in various HPC systems as well. For PCIe response vs routing through the CPU/OS, you see all sorts of offload engines and CPU bypass technology being used in networking stacks. For small IO being stored efficiently to minimize the lookup->retrieval process, data-on-metadata in Lustre (I'm sure other scale-out storage systems have similar implementations).

The march is of course to have the devices on the most high performance bus that makes sense from a cost efficiency standpoint, hence their mention of GenZ and similar technologies. We're definitely getting closer in the industry, I was just using an FPGA connected to a GenZ bus that exposed an NVMe device this week! Early prototype, but it worked in Ubuntu 18.04.