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Comment by CalChris | Hacker News Reader

I suppose if you used a minicomputer in the 70s or 80s then you used this or something like this chip. This is another site giving some more history and data sheets of the 74181 [1].

The carry-lookahead adder used in the 74181 was patented by IBM in 1957 [2].

Carry-lookahead is O(log n) in time and 0(n log n) in space. Carry-skip and carry-save are O(sqrt n) in time and O(n) in space [3].

I couldn't figure out what Intel or ARM or even RISC-V use. But according to this [4], full-lookahead for 32b is 5 gate latency while only being 4 times larger than ripple.

[1] https://apollo181.wixsite.com/apollo181/about

[2] https://patents.google.com/patent/US2966305

[3] https://booksite.elsevier.com/9780123838728/references/appen...

[4] http://www.cs.cornell.edu/courses/cs3410/2010sp/lecture/topi...

Does anyone know what Intel's Tiger Lake or ARM's A77 or RISC-V BOOM (and I looked at the Chisel source) use?

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> I suppose if you used a minicomputer in the 70s or 80s then you used this or something like this chip.

Most likely. What I liked about the old microcoded minicomputer designs back then was how accessible they were. The parts being fairly easy to understand with simple interfaces.

I'm not sure about the newer CPUs, and it's been a while since I looked at the die photos, but I believe the 8086/8088 use carry lookahead.

The Z80 uses a 4-bit "double-clocked" ripple-carry ALU: http://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-h...

Interestingly enough, the 8008 that came before all of those uses carry lookahead:

http://www.righto.com/2017/02/reverse-engineering-surprising...

You're confusing ISA with an implementation detail.

No, I really am not interested in ISAs at all. I'm interested in how various current microarchitectures (Tiger Lake, A77 or BOOM) implement add at the gate level.

I don't think that RISC-V is specified at the gate level. You don't want that if you are targeting FPGAs as the tools can't look at a tree of logical expressions in Verilog or VHDL and decide "oh you are designing an ALU" and map it onto the ALUs in a collection of slices.

RISC-V is an ISA. However, Berkeley BOOM is a microarchitecture, an out-of-order superscalar RISC-V core. It is synthesizable and parameterizable. While BOOM is primarily ASIC optimized, it is also usable on FPGAs.

https://boom-core.org/

But what I'm really interested in is which adder modern microarchitectures use.

As far as I know it's still good old carry lookahead, just with a lot more bits. The advances have come from multiplication and especially division; addition was figured out early on.

BOOM uses the rocketchip ALU, which uses the Chisel `+`, which probably compiles down to the verilog `+`, which probably gets synthesized to the appropriate width adder in the standard cell library of the vendor (e.g. TSMC or Xilinx). So for synthesized microarchitectures, it isn't determined in the RTL.

The context makes it clear that they used “RISC-V” as a shorthand for “modern, sophisticated implementations of RISC-V.”

Yes, we all know that you can implement RISC-V using a clever arrangement of turtles and that the resulting egg-gestation-based adder has no analog in electronic circuits. Moving on....

... or I could have checked the Chisel and Verilog source for several implementations.

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