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Comment by rjsw | Hacker News Reader

I don't think that RISC-V is specified at the gate level. You don't want that if you are targeting FPGAs as the tools can't look at a tree of logical expressions in Verilog or VHDL and decide "oh you are designing an ALU" and map it onto the ALUs in a collection of slices.

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RISC-V is an ISA. However, Berkeley BOOM is a microarchitecture, an out-of-order superscalar RISC-V core. It is synthesizable and parameterizable. While BOOM is primarily ASIC optimized, it is also usable on FPGAs.

https://boom-core.org/

But what I'm really interested in is which adder modern microarchitectures use.

As far as I know it's still good old carry lookahead, just with a lot more bits. The advances have come from multiplication and especially division; addition was figured out early on.

BOOM uses the rocketchip ALU, which uses the Chisel `+`, which probably compiles down to the verilog `+`, which probably gets synthesized to the appropriate width adder in the standard cell library of the vendor (e.g. TSMC or Xilinx). So for synthesized microarchitectures, it isn't determined in the RTL.

The context makes it clear that they used “RISC-V” as a shorthand for “modern, sophisticated implementations of RISC-V.”

Yes, we all know that you can implement RISC-V using a clever arrangement of turtles and that the resulting egg-gestation-based adder has no analog in electronic circuits. Moving on....

... or I could have checked the Chisel and Verilog source for several implementations.

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