The part you quoted is a part of a thought experiment. The author is explicitly saying that Verilog is _not_ an ISA:

> By way of contradiction, let’s imagine what it would look like if RTL were playing each of these roles well.

The point of this section was to point out that the set of people who use FPGAs as accelerators (a la MSFT catapult) use it with the ISA abstraction: they don’t want to care about he timing, they just want to get the dataflow graph to accelerate the computation.

Disclaimer: I work with the author of the article on acceleration architectures and languages.