We already pretty much do #1 & #4 today, it's call POP[1], take a look at a RPi3 and you can see the gap between the DRAM and SoC.
- The interconnect pitch is huge, 0.3mm-0.4mm. HBM memories have 1000s of I/Os
- The inductance of the solder balls and the impedance discontinuities in the path mean the logic below still has to have big energy-hungry I/O drivers
- If you want to stack more than one die, you need something expensive like through silicon vias (TSV)