I want to start by agreeing with you. It is true what you said about overclocking, chips that run cooler will be able to clock higher, and it is true that chips will disable sections of or even entire cores if they are un-used. So I don't know if you can measure this outside of validation setting. I think I have explained myself poorly so I will try again from a more technical perspective.

To drive the transistors in a chip you need to supply or sink enough charge so that the MOSFET will change state. The rate at which we can supply this charge places a fundamental limit on the switching speed of this transistor. Because until we overcome this charge requirement the transistor will not turn on/off.

Now the speed we can move this charge in and out of the input of the chip is governed by resistance. Higher resistance between VCC and the gate means it takes longer to over come the capacitance and change the state of the MOSFET.

Lets say for some given arbitrary Transistor its input capacitance is some 50pF , and lets also say our resistance to vcc is 10 ohm, then tao or the time constant is nothing but RC or 500 pico-seconds. In other words the maximum switching speed that we can see on the output is 1/tao or some 2Ghz. Now logic circuits are more than one transistor deep, and we can't reasonably run the circuit at exactly tao (Also at t=tao the gate is not exactly vcc it is ~.63vcc as this is an exponential function) and expect any level of signal integrity. But this tao is sort of a hard limit to switching speed as it is the time it takes the transistor to swap state.

In some sense low resistance is a boon. Low resistance means low tao, as tao is just RC. If tao is small than the transistor changes state more quickly. As a result for a given clock, the transistor has longer to overcome any inductance/capacitance present and is able to emit a cleaner signal.

But what lower resistance means is that you have higher power consumption as: p=iv & v=ir -> P=V^2/R So we see low resistance-> higher current. and higher current -> more power.

So we see it is a balancing act. We can have higher speeds or we can have lower power but not both. So if we are binning for a certain speed we are also binning for a certain power consumption characteristic. By selecting chips with speeds greater than XGhz we are also selecting chips with internal resistance < R.

Now what you said about over clocking is true. But because of an added twist.

Say we are binning a set of R that satisfy clk > XGhz. So naturally some subset of R will still be comfortably capable of XGhz while using less power than the average member of R. Now the chip has real limits to its capability to perform while hot. So this subset performs well as it is just low enough resistance to run a XGhz while limiting power use. On the high edge of the set R, we see chips that barely made XGhz and cant clock better. On the low edge of set R we see chips that are runing so hot as to barely maintain XGhz. So there is a sweet spot.