> I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications.
Probably because it has very limited support in open source tooling, same as VHDL.
Probably because it has very limited support in open source tooling, same as VHDL.
Yosys (which AFAIK is still the only non-toy open source synthesis tool) supports a _very_ small subset of SV, and does not support VHDL (at least in the open source version).