Spartan-6 does not.
But Xilinx has a MIG (memory interface generator) that automatically creates the RTL for a memory controller that synthesizes to regular core logic.
In addition, it also has IO cells with posedge and negedge FFs and calibrated delay lines.
Getting the DDR DRAM to work on the Pano G2 shouldn’t be too hard. (Less hard than the G1, which has DRAM that isn’t supported by the MIG.)
I really should get the DRAM working on the G2. How hard could it be?
Just got it up and running with a 125MHz clock and the Xilinx MIG (memory interface generator.)
I used a similar DDR2 memory (MT47H64M16 I think) on a Cyclone III a few year ago. Using the ALTMEMPHY from Altera it was not to difficult to make it work. Then later we got a new batch of cards witch would randomly fail. The problem was that DDR had been switched from Micron to an equivalent from Samsung. But the timing must have been just different enough to cause random fails. So yes DDR2 memories can be tricky.
Many years ago at University I used Leon and grlib for a project. It was a nice processor and IP library. I would like to use it again.
[1] https://www.xilinx.com/support/documentation/data_sheets/ds1...