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dwoozle

You mean the multi tens of thousand dollar FPGA set up that Xilinx hawks doesn’t have source control?

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Commercial FPGA tools are a joke. I really hope SymbiFlow [1][2] will make the development experience way better.

[1] https://symbiflow.github.io

[2] https://github.com/SymbiFlow

I understand there is some validity with this criticism. Xilinx has always been slow to adopt standard software development practices. But really, Xilinx tools have never cost 'multi-tens of thousand dollar's. The most expensive tools are several thousand dollars. There are also free tools for smaller devices / certain flows. Source control is done with tcl scripting (simple text files) and standard source control tools. It's not as bad as it was in the past. Cheers.

Microsemi Libero is a joke and is probably the greatest hindrance to getting actual work done. I wish Xilinx bought them out instead of Microchip so there could actually be some improvement to the tools. You can throw every bit of computing resource at it's dinosaur PnR tool and it will just happily chug along at 1% CPU usage. They just came out with some update that made a 20% improvement to PnR, literally hours of time gained back from watching a wheel spin. What is it doing? Who knows, it will probably fail and not tell you why. Zero source control, almost zero documentation for scripting, and a design tool that seems nearly crash everything just to tell you there are IP core updates available.

The only parts that actually work reliably are whatever ancient Actel-branded tools are hidden in the suite.

This is one of the reasons I jumped ship from writing VHDL for Xilinx parts and am now a Java dev. It’s worth noting that Altera, the other major FPGA vendor, is not noticeably better in this regard (or at least they weren’t when I last used their stuff ~5 years ago).

(The other reason is that I am unbelievably bad at getting the damn thing to meet timing.)

So every time you compile/synthesize the result is different?

Not with the same exact source files / same software version. But sometimes small changes in the design, or changing tool versions can cause the design to not meet timing. It's just the nature of map / place and route.

It often is. Place-and-route is typically implemented as simulated annealing, which is a randomized algorithm. Unless you explicitly force it to reuse the same seed, you'll get slightly different results each time -- and even if you do set a seed, small changes to the HDL may result in a vastly different result.

People like to lambast "enterprisey" software on HN, but it's got nothing on the typical software written by a hardware company.

In their defense, nobody is buying FPGAs for the tooling, so "just good enough to check the boxes" is probably the correct economic decision with the current state of affairs, since it's probably 10x as expensive to write software that is actually pleasant to use, and while they sell a lot of FPGAs, they don't sell very many FPGA dev tools, so the economies of scale aren't there.

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