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Comment by Tuna-Fish | Hacker News Reader

The RISC-V ISA is pretty awful for high-end designs. No competitive servers can be built with it.

Plenty of people seem to have been caught up in the hype of RISC-V taking over the world and doing everything, but that's never going to happen. The ISA is heavily optimized towards making very low-end devices very cheap. Like, don't think cellphone chips, think appliances. This is not a bad call, as it's the area where greenfield designs with cost advantage have the best chance to get market share. However, there is no path of extending the ISA that will make it competitive with ARM or x86 on high-end devices. The only way to do that is to design RISC-VI, that abandons most of the things that RISC-V what it is.

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> The RISC-V ISA is pretty awful for high-end designs. No competitive servers can be built with it.

I have to dispute this. RISC-V was specifically intended to make high-end designs (i.e. out-of-order architectures, multicore, SMT etc.) not just feasible but relatively easy. It's also designed for extensibility from the ground up, which few others architectures are.

Interesting view. The SIMD, Vector, and Hypervisor RISCV extensions, as well as things like OoOE seem to contradict your claim. Are you saying they intended to target the high end, and failed? Or that they never intended to target the high end?

There are a lot of things about the RISCV design that come from a very ideological place and hurt in a high end design. Yes, there are extensions and designs with high end features, that's certainly true, and I'm sure people someone will be making a high end version at some point. But the ISA isn't very well suited to it compared to Power or ARM.

By default, code density on RISC-V is pretty bad. You can try to solve that by using variable length instructions which many high end RISC-V projects intend to do but having variable length instructions means your front end is going to have to be more complicated to reach the same level of performance that a fixed width instruction machine can achieve.

More instructions for a task means your back end also has to execute more instructions to reach the same level of performance. One way to do better is to fuse together ISA-level instructions into a smaller number of more complex instructions that get executed in your core. This is something that basically every high end design does but RISC-V would have to do it far more extensively than other architectures to achieve a similar level of density on the back end which makes designing a high end core more complex and possibly uses extra pipeline stages making mispredicts more costly.

And more more criticisms here: https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d99...

EDIT: But in fairness it looks like conditional move might be getting added to the bit manipulation RISC-V extension which would fix one big pain point.

This isn't to say that RISC-V is bad. It's simplicity makes it wonderful for low end designs. It's extensibility makes it great for higher level embedded uses where you might want to add some instruction that makes your life easier for your hard driver controller or whatever in a way that would require a very expensive architecture license if you were using ARM. It's open, which would be great if you were making a high end open-source core for other people to use except the Power ISA just opened up so if I were to start a project like that I'd use that instead.

> By default, code density on RISC-V is pretty bad.

Code density with the C extension is competitive with x86, which is very good for a RISC. And the C extension is not even that hard on the decoder, since most or even all 'compressed' instructions have a single uncompressed counterpart. It's easier to implement than what ARM32 does with Thumb.

> One way to do better is to fuse together ISA-level instructions into a smaller number of more complex instructions that get executed in your core.

Insn fusion has in fact been endorsed by the designers of RISC-V as an expected approach in high-end designs. The RISC-V spec even gives "suggested" sequences for things like overflow checking, that can be transparently insn-fused if an implementation supports it.

Yes, RISC-V's instruction compression is easier to use than Thumb. But there's a reason no arm server uses compressed instructions and ARM dropped it from A64.

Enlighten us: what is that reason?

As far as I can tell the reason is that with variable length instructions you have a mux layer between fetch and decode that sends the right set of bytes to the right decode slot. Your first set of 16 bits is certainly going into the first decoder but your fourth might be going to the second, third, or fourth depending on previous decoding. Or maybe not, I've only worked with fixed width instructions when getting into the weeds of processors and only entirely designed a simple five stage classic RISC myself. So don't take the above too seriously.

What you should take seriously is that three of the four big RISC ISAs - MIPS, ARM, and POWER - all have extensions for variable length instructions. They all use them in embedded systems where program memory size is a big factor in your bill of materials and reducing that can save you money. But none of them use it on their high end processors. So I think we can conclude that the power/transistor cost of fetching a number of variable length instructions per clock is higher than the cost of expanding the L1 instruction cache to deal with full size instructions.

At most, you're looking at an extra pipeline stage for all of that. The less I$ pressure is almost certainly worth it.

The real cost you're looking at is the complexity for instructions to straddle cache lines and MMU pages, but even then it's less of a deal than you might think.

Nope, done right the cost is a layer of 2:1 muxes and some control logic to pass data between decoders, and 16 flops to hold a partially decoded instruction between fetch bundles

For sure, it's just that this little bit could necessitate a pipeline stage if that was the critical timing path somehow already. Just trying to be as friendly to their argument as possible before taking it on.

It's more complicated than that if you want to decode multiple instructions per cycles, which you have to for high-end designs. I still agree with monocasa that it's almost certainly going to be worth it for the reduced I$ pressure.

Thumb works as an alternative encoding that you have to switch to and where you just have a subset of the instructions available. Switching has at least the same cost as a branch. My guess is that this is the reason why thumb is avoided often.

RISC-V on the other hand has an encoding scheme that already from the beginning allowed instructions with longer and shorter encodings. You can just mix compressed instructions with normal ones.

x64 has that problem, in the extreme (max length of an instruction is 15 bytes) doesn’t it?

It must be a pain to design its instruction decoder, but I don’t think that’s insurmountable for high end processors.

Or do I misunderstand your argument?

Yes, it certainly does. As far as I can tell it takes more engineer hours to make an efficient x86 front end than it does a RISC front end and the RISC designs I see tend to balance their pipelines so that they're wider in front than x86 designs typically are. Everything here is a matter of "all else being equal" and the talent and hard work of the design team are more important than any of the ISA differences we're talking about here.

Thank you for clarifying. It still seems wrong, somehow. Admittedly I don't know enough detail about Thumb and the others, but if the variable-length encoding is a simple design like RISC-V's, it's hard to imagine that extra layer to be so expensive as to eliminate the benefits of an effectively increased I$. It would be nice to be able to dig deeper into the details of this.

I don't think it's as easy as saying that Aarch64 dropped thumb, therefore compressed instructions are dumb.

- Like somebody already pointed out, thumb is a different mode, whereas RISC-V C (RVC) can be freely mixed with normal 32-bit instructions.

- And speaking of higher end processors, x86 does very well in that space despite requiring much more complex decode than RVC.

- Aarch64 has more complex addressing modes (base + index<<shift in particular) whereas RISC-V needs both RVC and fusion to do the same with similar code size and execution slot occupation. Personally, I'm leaving towards thinking that it was a mistake for RISC-V to not support such addressing modes. Unless you're aiming for something really super-constrained in terms of gate counts, having an adder and small shifter as part of your memory pipeline(s) seem like an obvious choice. And thus, having single instructions to use those pipelines isn't really committing any sins against the RISC philosophy.

That’s funny, SiFive just announced a 3-way OoO RISC-V core. A73 performance, but half the die area. Pretty awful, I guess.

https://www.sifive.com/blog/incredibly-scalable-high-perform...

FYI the comparison is to the A72, not A73.

A72 is a mobile chip, so still not particularly relevant to tuna-fish's claim about high end servers. The raspberry pi 4 is not a high end server.

> half the die area

Much of this is free when comparing a 16nm design to a 7nm design. See footnote 1 in your link.

EDIT: I was curious, so I looked up the transistor density of tsmc 16nm vs 7nm.

16nm: 28.8 MTr/mm^2

7nm: 96.5 MTr/mm^2

So I think that sifive core with "half the area" is actually not quite as good as a die shrink of the A72.

>> A72 is a mobile chip

So is Apple A13. And yet it's been reported to outperform all Intel desktop CPUs in single core performance (I find the benchmark dubious, but I do believe it's close, and faster than it has any right to be given the super low power consumption). The only reason it doesn't do so in multicore perf is the limited TDP - a concern which does not exist in high end chips.

https://news.ycombinator.com/item?id=21033371

Sure. Even all of Apple's macOS-Server machines running the Apple Cloud are powered by A13 chips these days. /s

Non sequitur.

Necro-reply here, but yes you got me. 2.63mm2 on 7nm is about 8mm2 on 16nm, which is same as the A72. And it was the A72, the A73's predecessor. I think the point stands that RISC-V is suited for high-performance designs, which was the original contention. If a startup can do 3-way OoO, an org with more resources can do 7-way OoO along with more sophisticated branch prediction and stronger cache coherency to catch up to state-of-the-art cores. There isn't anything in the RISC-V ISA preventing that.

This argument would benefit from specific examples.

You've not justified this. I'd be very interested in understanding why you make this claim.

> No competitive servers can be built with it.

Not all servers need to be high end. There’s a big market for small websites.

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