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How exactly does this work? Is it a poor man’s FPGA?

It's a standardized design for chip manufacturers to make it easier for them to add custom instructions in hardware to an ARM core and provide toolchain-support for it, not something software-programmable for the end-user.

Since op mentioned FPGAs:

Do you recall NIOS custom instructions? It's similar to that in many aspects.

They exposed a bus on one of their Cortex-M cores, so you can add custom instructions when building an ASIC.

Perhaps more importantly, they also changed their licensing to allow custom instructions.

The bus thing sounds like coprocessors on x86 up to and including 386 (though presumably not in separate chips here).

Later there was no real bus anymore (486 SX "FPU" replaced the main CPU) or the only(?) kind of coprocessor ever used, the FPU, became integrated into the CPU.

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