But, I absolutely love the concept of chiplets and can see a trivial 10x in logical transistor density, even if we don't shrink the process nodes any further or even make major changes to the current generation of chiplet-based CPUs.
We are currently only arranging these things in 2D. If AMD/TSMC develop a way to stack chiplets in 3 dimensions, we could wind up with another huge bump in logical transistor density per socket/node.
Chiplets are ultimately about solving the manufacturing and business problem of defect density. There isn't much additional magic going on here in terms of beating Moore's law.