I've always wanted to do exactly what you just described! Can you recommend any resources to get started with FPGA design for a software dev?
[1]: https://sigrok.org/
[2]: https://www.aliexpress.com/item/32877931876.html (random seller link)
The iCE40 FPGAs are a bit whimpy compared to Altera and Xilinx offerings from what I understand, but I really liked the idea of an open-source toolchain[3][4] being available.
To get a taste without committing cash you could just use a simulator[5], which I imagine you'd be using a fair bit anyway as it allows you easier access to the internal state.
As to actually programming, I've found the following resources useful. I started with Verilog mainly because code-gen tools like nMigen[6] generate Verilog, but for writing by hand it seems VHDL is preferred.
Anyway, links, first off some exercises to get going[7]. Introduction to Verilog[8], also has a nice general overview of HDL. Details of how non-blocking vs blocking statements in Verilog works[9], quite specific but was very informative for me.
There's also quite a lot of activity over at Reddit[10], and good experiences over at the EEVBlog forums[11].
As I said I just got started so no expert yet :)
[1]: https://www.digikey.com/product-detail/en/lattice-semiconduc...
[2]: https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards
[3]: https://symbiflow.github.io/
[4]: https://github.com/cliffordwolf/icestorm
[5]: http://iverilog.icarus.com/
[6]: https://nmigen.org
[7]: https://www.fpga4fun.com/
[8]: https://www.chipverify.com/verilog/verilog-tutorial
[9]: http://sunburst-design.com/papers/CummingsSNUG2002Boston_NBA...
Also it's very important to keep in mind that HDLs describe hardware, the HDL code is not executed on the hardware. Think of it as writing C++ templates.
So if you want to stick with FOSS tools, then you're stuck with synthesizable Verilog-2005 at best, for the moment. And standard Verilog very much sucks in a lot of ways, I would argue, synthesizable subset or not. It's an understandable choice though, in a field full of awful options. One day I'm hopeful Yosys will support most of the necessary SystemVerilog features people want for synthesis... (Then, it can also serve as an effective SystemVerilog -> Verilog translation tool, which would be very useful on its own.)
Additionally, I'd like to clarify that nMigen generates Verilog indirectly; it actually generates RTLIL, which is the intermediate representation of Yosys, and then Yosys turns it into Verilog after some cleanup passes.
I'll happily admit to being biased, but nMigen is so much easier for me to work in than Verilog ever was.
Hadn't quite gotten the connection with Yosys right yet, as I haven't yet started with nMigen, but yeah I definitely want to go there. But like I said, I prefer getting a good handle on Verilog first so I know what to look for when things go wrong.
I was inspired to all of this by the YouTube video series by Robert Baruch[1], where he tries to recreate the 6800 CPU on a FPGA using nMigen with formal verification.
[1]: https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPS...