I’m sure Google and others have evaluated this, but it’s just kind of surprising that they opt to do per-packet processing in software.
Disclaimer: I write router software at Cisco.
https://cloud.google.com/blog/products/networking/google-clo...
https://cloud.google.com/security/encryption-in-transit/appl...
Regarding your points: I am not sure I completely follow.
Firstly, as far as I know, Google does not make its own switching or routing ASICs.
Secondly, virtually all switching and routing ASICs are highly programmable. So if you need a custom protocol, you can implement it using the vendor’s microcode (e.g., P4). In other words, you are not limited to the protocols that the vendor has implemented.
Given the above, I don’t see what kind of technical requirements Google has that would disqualify the use of routing ASICs.
But from just the bandwidth and latency perspective, a custom ASIC makes more sense to me.
giving credit where it is due, intel's role in development of latest pcie-4.0 and upcoming pcie-5.0 specs and ofcourse the latest cpu's make it less and less appealing to consider putting up with custom h/w + s/w imho
with dpdk for example, doing 10g/core with 64b packet sizes is considered pretty standard these days. and if you don't want to roll your own, you always have companies like 6wind to help you (and ofcourse they share the code as well)
facebook/google etc. have, by now, probably at least a decade of experience running their own sdn enabled networks. facebook even has fboss to commoditize switch from white-label manufacturers...
Even if you utilize every last cycle of CPU, the price/bps and energy/bit will still be way higher than almost any switching or routing ASIC on the market.