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Comment by sweden | Hacker News Reader

As a hardware designer (well, mostly a hardware verification engineer), I feel that this kind of comment is a pure misconception from software people that gets echoed time after time in HN.

I generally see a lot of more effort and good quality tools in hardware verification than in software validation. The hardware design and verification industry is not really 30 years behind the curve compared to software development.

Hardware and software are two very different problems with their own set of constraints. It's actually more often that you see software barely tested being deployed in the wild to millions of users rather than hardware. Hardware bugs tend to get more attention because you can't really deploy a patch to fix the issue.

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Having worked with both HDLs and software tooling, I don't think it's too far off the mark. HDL tooling is terrible software: it's hard to use, buggy, expensive, opaque, and the support is terrible unless you're a huge customer. Hardware verification and development works still through sheer effort, and because there's a strong business incentive to get things right the first time due to the huge costs of a respin. With better tools this could be done faster and cheaper with similar reliability, but perhaps there isn't enough to be gained to make it worth the effort (and either way I don't think the companies currently working on the tooling are capable of making anything else: this would need disruption to really make a difference, and the barriers to entry are huge).

We get decent support from our main tooling providers. We do spend a chunk on licenses but I don't think we'd be considered a huge customer. And yes, the software has bugs (with expensive consequences) so good support is very important.

Hardware design flows are complex and do have bugs, but not in the way it sounds. In general HDL synthesis produces a design that matches what the user wrote, so a logic bug in a synthesis engine is rare. The bugs exist in the 'other stuff', like trying to convince the tool to be efficient about how it created the design, or smart about how it's trying to close timing. Getting a working though the tools design is easy, getting an optimal design is hard. HDLs themselves have issues, but there is a wealth of quality checking tools built around them that mitigate them, and indeed mitigate/flag poor coding from inexperienced designers (to a degree). What's interesting is FPGA tools, as much as they are derieded, are much better than their Asic counterparts in terms of functionality and user friendliness.

> I feel that this kind of comment is a pure misconception from software people that gets echoed time after time in HN.

but this is NOT a misconception. Show them actual tools that constantly crash and lag on you, that demand checking out licence for a runtime which costs 5-100k/Year, show them environment in which we have to write our code - they will laugh at you. This was exactly the state of the software industry 30 years ago and this industry is long past that stage.

Those are some very empty counter arguments but I will try to answer them anyway.

EDA tools are expensive, yes. But you are not just paying for the tools, you are paying for all the engineering support being those tools. Bugs and problems happen in any development tool and those companies are ready to pick up the phone at any time of the day to help you with anything you might face, whether it is a problem with their tool or a problem with their setup, to the point that they can deploy a new version of their software on the spot just for you.

And they have actual engineers on the other end of the line who know the product like the palm of their hand.

While this might sound superficial, it is extremely important when you are racing towards a $100M dollar deadline for your project.

> EDA tools are expensive, yes. But you are not just paying for the tools, you are paying for all the engineering support being those tools.

So I can buy the tool without the support contract?

> Bugs and problems happen in any development tool [...]

So it's automatically a wash? Why bother trying to improve things if there will always be bugs, right?

> [...] whether it is a problem with their tool or a problem with their setup, to the point that they can deploy a new version of their software on the spot just for you.

I'm not impressed. This is a kludge.

> And they have actual engineers on the other end of the line who know the product like the palm of their hand.

Okay, that actually sounds pretty nice.

> So I can buy the tool without the support contract?

Probably not but it's not something you would like to. Cutting corners is a really bad idea when it comes to hardware development because once it is out there, there is not going back.

Having access to a professional engineering work force that knows how the tool works and know it will ready and interpret the Verilog and process it can make a difference between a 5 minutes delay and 2 week delay in the project.

> So it's automatically a wash? Why bother trying to improve things if there will always be bugs, right?

You are distorting my words. I'm not saying that we should be complacent and just accept incompetence.

>> [...] whether it is a problem with their tool or a problem with their setup, to the point that they can deploy a new version of their software on the spot just for you.

> I'm not impressed. This is a kludge.

So how would you handle it? Tell the customer you'd love to fix their problem but they have to wait for the next formal release?

The level of quirkiness and bugginess in the tools is on another level to most software tools. You shouldn't need access to the engineers who built it in order to make it work, this basically increases costs and barrier to entry massively.

Many of the tools are bleeding edge, developing new features to support a new process node at the same time as the new process node is being developed.

This doesn't seem relevant to most of the tooling, which is not bleeding edge, and should be mature.

Certainly on the simulator/synthesis side you can still encounter straight-forward bugs in SystemVerilog features that were standardized over a decade ago (or find they're not implemented at all) or even simple parsing bugs (the kinds of bugs that would be trivial to find with some decent randomised testing of the parser).

Things being bleeding edge and fast evolving in certainly true for some EDA tools or parts of them but there's lots of more bread and butter stuff that never feels quite right.

That is no excuse. A lot of software out there is bleeding edge, yet costumers do not tolerate crashes.

Sure, that's why important software never crashes. /sarcasm

And... it does not. Most crashes in actually important software are due to hardware/memory errors, rather than the software itself.

Of course, I hope you are not referring to Windows or any day-to-day software by "important".

> The level of quirkiness and bugginess in the tools is on another level to most software tools. You shouldn't need access to the engineers who built it in order to make it work, this basically increases costs and barrier to entry massively.

I do not know what SW tools are you using but i'm still looking forward for a SW tool that doesn"t suck.

Oh yeah, software tooling also sucks, I'm just saying it's on average still better than the best of any hardware tooling I've ever had to use.

I believe software developers are split between IntelliJ, Eclipse, Visual Studio and VS Code. They do work very well compared to what I've seen in the embedded world.

Ignoring text editors here, because text editors are not programming environments (no debugger, no compiler, no source control, etc...)

I mean, this sounds a lot like software 20 years ago.

You can still get proper support for, say, IntelliJ if you want it, but tools and ecosystem have improved so much that it’s just not as important as it used to be.

To be clear, I’m not claiming that hardware development is the same as software development. It’s not. It has different problems. But the tooling _does_ seem well behind.

> You can still get proper support for, say, IntelliJ if you want it, but tools and ecosystem have improved so much that it’s just not as important as it used to be.

How many people are doing hardware verification work vs. cranking out webapps with IntelliJ?

JetBrains can invest a lot in software ergonomics because they're basically selling mass-market software. If you have sophisticated but niche software, your probably going to invest your engineering effort into the it's capability rather than its ergonomics.

I mean, to take one example of a company in the space: Xilinx has operating income of about 750mn per year. Jetbrains has operating income of about 80mn per year on revenues of 250mn.

Given that I’d suggest that the reason that Xilinx’s development products have such a poor user experience vs IntelliJ is NOT that Xilinx is impoverished, but rather that the market has extremely low expectations so they don’t feel the need to spend on fixing them.

This isn’t a problem unique to hardware-land; lots of verticals have incumbents who produce low quality products on large profits because, frankly, the competition is just as bad and there’s a high barrier to entry. I’m not sure what would fix this for hardware-land, though. Possibly more pressure from open source; that’s largely what did it for software development (though even before that, companies like Borland put more than the minimum effort in).

Xilinx are not just writing software, they also must use R&D to develop the FPGA hardware, dev kits, IP, etc, so it's a very different scale to JetBrains' focus. Also in terms of Sofware, the really challenging aspects are under the hood, the place and route algorithms, the static timing engine, the system verilog simulator (which is itself a huge undertaking), the hardware debug cores, the HLS SW that compiles C to accelerated HW, then SDK for embedded processors, oh.. And of course... Finally the GUI/IDE. With all that's going on underneath, Vivado does a decent job of presenting it all in a logical way. I'm blown away that I can see a timing failure on any of a million nets and in a click cros probe it to a line of verilog.

As for open source, SystemVerilog is an open standard, yet can you show me an open source simulator that competes with the free one that comes with Vivado?

On the one hand Vivado is not entirely terrible considering that it can get some work done, but on the other hand it's beyond me why it's lacking the most basic needs of software development.

Zero support for source control? SoC have no examples, why can't they systematically provide an hello world example (blink a LED) with their development boards? The IDE itself has close to zero doc and there is no help on the internet, it takes 3 freaking days for an experienced developer to figure out how to create a project.

Theres a load of documentation, videos and examples, both on github maintained by xilinx as well as on xilinx.com. For example: https://www.xilinx.com/support/university.html and linked from there is a complete course in getting started with all materials, slides and docs : https://www.xilinx.com/support/university/vivado/vivado-work...

Have you used software verification tools? They're almost universally terrible. In many cases incomprehensibly so. Many are free up front, but you pay for it one way or another. The level of sophistication and workflow integration of software verification tools, compared to hardware verification tools, also seems to lag significantly.

I don't doubt that the hardware verification tools are expensive, buggy, and probably have terrible UX. However, all those things are also true of software verification tools, but where license cost is replaced by esoteria and incompleteness cost.

Valgrind is pretty robust and I've seen it integrated into many projects with little fanfare. Unit tests are just simulation runs.

I've done VHDL/Verilog and tons of software, the HW tools do lag significantly in my experience.

Valgrind is not in the class of verification tools I was referencing. How does it correlate to VHDL/Verilog in this context? I would expect things like MBD tools, model checkers, and proof assistants, and program extractors to be the software pipeline siblings to the kinds of tools that VHDL/Verilog integrate with.

It's a tool to verify the software runs correctly and doesn't double free, write over the heap and a while bunch of failure. Unless you never run simulation and always trust the router?

Not everything gets verified 100% in HW, otherwise we wouldn't have silicon errata. It's all a question of how deep you want to go in verification and what your costs are for screwing it up.

I don't agree. I agree that if compare random software project x to a random hardware project y that the hardware project will do a lot more verification.

But that doesn't really compare to state of the art of what's possible in software. Property based testing, symbolic execution etc all have incredible power that afaik is not available in the hardware world. I'm just a hobbyist who uses FPGA's but it's way way easier for me to ensure a function has some properties compared to a VHDL module or whatever.

> I feel that this kind of comment is a pure misconception from software people that gets echoed time after time in HN.

But the comment came from a hardware designer, at least the grandparent one (from artemonster)?

Yes, hardware must be right first time. Proving that is difficult, so logic equivalence, formal proof, code coverage are all standard. What's optional in many software QA flows would be absolutely required in HW flows. Proof of functionality is paramount

> I feel that this kind of comment is a pure misconception from software people

I really hoped you were referring to the secrecy

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