Building a ternary computer at home: a software emulator
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I once tried using ternary to explain to a semi-retired mainframe programmer how we wanted to modify a binary field to have more than two choices. He was so mad and insisted you can't just MAKE UP MATH when explaining your project goals. This project would have made his head explode.
Unless you've been burned by that before and remember to check those assumptions.
As far as practical applications of non-binary circuitry, the Intel 8087 math co-processor used 4-level circuitry in its ROM. (This chip was used in the IBM PC.) Intel needed to do this to fit the large microcode ROM on the chip. The chip's logic, though, was regular binary. http://www.righto.com/2018/09/two-bits-per-transistor-high-d...
Also, as noted at the bottom of that article, most modern flash storage uses multi-level cell technologies that allow two, three, or four bits of data to be stored per memory cell rather than just one. This obviously significantly increases data density and allows for cheaper drives at the cost of reduced write performance, reduced endurance, and more error correction being necessary for reliable operation.
How do you make ternary gates out of a DG403? (It’s an analog switch that would pass ternary, but the switch control inputs are binary.)
https://hsto.org/webt/4a/mb/ad/4ambad_bocdk6_0khdqve6grzjs.p...
two ternary multiplexers out of two dg403 chips.
I found that ‘4’ a weird choice for a ternary computer, until I read that R1 is special.
Register-to-register moves always involve R1. There are 12 such moves into R1 and 12 out of R1. That leaves 3 trit patterns in a 3-trit value for “increment R1”, “decrement R1” and “NOP”.
Also, this architecture doesn’t allow reading data from, or writing data to memory. The memory only is there for storing. programs. So, it’s almost as if this has one register, 12 words of data memory and 729 words of program memory.
Weird, but economical on the hardware, I guess, so it keeps the cost and amount of work down. Also, there’s room for extension commands, so the above may change.
I know we are doing this for SSDs but they're simple and (mostly) homogeneous.
Think about it this way: as the number of states approaches infinity, you're back to analog computing.
It's a design parameter, not something that lets us break past limits on computational density, which right now is heat removal and quantum tunneling in transistors.
[1] If memory servers, adders and cache access and a bunch of other logic typically require O(nlog₂n) gates in binary, but O(nlog₃n) in ternary, Which means as the native integer size increases, bases greater than 2 scale better.
Don't know if any of that has made it into the literature, but you could have a look.
[1] Hayes, B. (2001). Third base. American Scientist 89: 490-494 (http://lrss.fri.uni-lj.si/sl/teaching/ont/lectures/third_bas...)
Anyway, if ternary is actually optional in practice depends as much on how efficient the ternary logic can be implemented on a silicon process. If you increase integer storage efficiency by 10%, but circuit density decreases, maybe you're not getting enough value.
By the time someone built a base 20 computer it would probably be an anachronism anyway.
It's true that you can conveniently represent the numbers by using integer powers of the base (like representing binary with hexadecimal), but the whole reason e is a "good" base in the first place is because you're (partially) minimizing the number of distinct symbols needed to represent a number, and you lose that once you go to a higher base.
Plus, using a slightly-off integer like 7 breaks the integer-power-mapping anyway.
[1] x ^ (N/x) for any N.
The most notable of these is Setun' (I had a chance to play with it at Moscow State University).
[0] https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=2009020829793...
[0] https://wwwee.ee.bgu.ac.il/~kushnero/ternary/Using%20CMOS%20...