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I don't think so, because CMOS circuits are not restricted to being series-parallel like, as in logic expressions. For example, one can implement, e.g. not(AB+CD+E(A+C)(B+D)) with just five gates (one per input) for each of the direct (pull-down) and complementary (pull-up) network.

This makes sense when comparing the instruction set to the logic circuit of the 74181! So many seemingly complex instructions for such a simple circuit :). Thank you for pointing this out!

74181 is based on TTL logic not CMOS, but you're right that similar considerations can apply to a higher-level logic circuit, and that these explain how "seemingly complex" can in fact be quite simple.

You can minimise the number of gates but that doesn't minimise the number of transistors as that varies by the type of logical operation performed by the gate.

Practically you probably care more about the number of transistors than the number of gates.

Depends on which gates you allow in your design. But the SMT encoding is really flexible, so you can adjust it for your needs.